Conferences related to On-chip Pvt Sensing Circuits

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)

This conference is a forum for researchers and designers to present and discuss variousaspects of VLSI design, EDA, embedded systems, and enabling technologies. The program willconsist of regular paper sessions, special sessions, embedded tutorials, panel discussions,design contest, industrial exhibits and tutorials. This is the premier conference/exhibition in thisarea in India, attracting designers, EDA professionals, and EDA tool users. The programcommittee for the conference has a significant representation from the EDA researchcommunity and a large fraction of the papers published in this conference are EDA-related


2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)

The IEEE International Midwest Symposium on Circuits and Systems is the oldest IEEE sponsored or co-sponsored conference in the area of analog and digital circuits and systems. Traditional lecture and interactive lecture/poster sessions cover virtually every area of electronic circuits and systems in all fields of interest to IEEE.


2018 24th International Conference on Automation and Computing (ICAC)

The scope of the conference covers a broad spectrum of areas with multi-disciplinary interests in the fields of automation, control engineering, computing and information systems, ranging from fundamental research to real-world applications.


2018 31st IEEE International System-on-Chip Conference (SOCC)

System on Chip


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Periodicals related to On-chip Pvt Sensing Circuits

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Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Lightwave Technology, Journal of

All aspects of optical guided-wave science, technology, and engineering in the areas of fiber and cable technologies; active and passive guided-wave componentry (light sources, detectors, repeaters, switches, fiber sensors, etc.); integrated optics and optoelectronics; systems and subsystems; new applications; and unique field trials.


Magnetics, IEEE Transactions on

Science and technology related to the basic physics and engineering of magnetism, magnetic materials, applied magnetics, magnetic devices, and magnetic data storage. The Transactions publishes scholarly articles of archival value as well as tutorial expositions and critical reviews of classical subjects and topics of current interest.


Sensors Journal, IEEE

The Field of Interest of the IEEE Sensors Journal is the science and applications of sensing phenomena, including theory, design, and application of devices for sensing and transducing physical, chemical, and biological phenomena. The emphasis is on the electronics, physics, biology, and intelligence aspects of sensors and integrated sensor-actuators. (IEEE Guide for Authors) (The fields of interest of the IEEE ...


Systems Journal, IEEE

This publication provides a systems-level, focused forum for application-oriented manuscripts that address complex systems and system-of-systems of national and global significance.


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Most published Xplore authors for On-chip Pvt Sensing Circuits

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Xplore Articles related to On-chip Pvt Sensing Circuits

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CMOS mixed signal SoC for low-side current sensing

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017

A switched capacitor low-side current sensing signal conditioning circuit with high dynamic range is demonstrated in AMS 0.35 μm, 3.3 V CMOS process. The design incorporates a Switched Capacitor Programmable Gain Amplifier (SC-PGA) and multi-bit second order ΔΣ-ADC. The switched capacitor eliminates the need for explicit level-shifting and chopping circuits thus facilitating sensing of input signal with zero common-mode. Both ...


On-chip PVT compensation technology for adaptive voltage scaling control in computer power management application

18th International Conference on Automation and Computing (ICAC), 2012

Power efficiency has become a major issue in computer Power Management Unit (PMU) as modern Integral Circuit (IC) is scaling toward smaller feature size. In high-performance computing applications, PMU electronics suffer from extensive Process-Voltage-Temperature (PVT) variation since high-level integration has exceeded physical limit of semiconductor material. This paper provides an overview of adaptive powerperformance management with emphasis on design optimization ...


A low power, moderate accurate, single stage driver circuit for on-chip voltage regulator

48th Midwest Symposium on Circuits and Systems, 2005., 2005

A new single stage driver circuit with improved load regulation is proposed for an on-chip voltage regulator. A load sensing circuit for low static power under light load conditions is also proposed. Lastly, a new coupling technique is proposed for improved transient and stability performance of the regulator


Low cost low power POR circuit for low voltage sensing using adaptive bulk biasing

2016 11th International Conference on Industrial and Information Systems (ICIIS), 2016

Many VLSI application system operate I/O supplies and core supplies and follow a predefined power up sequence. In this paper, a technique is presented to design low cost low power on reset circuit targeting low power applications. For designs operating on two supply (IOs etc.), most of the application requires power supply sequence free implementation and in order to do ...


Output buffer with self-adjusting slew rate and on-chip compensation

Proceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211), 1998

In this paper, two circuits are proposed to effectively control IC noise. The first circuit is a modified I/O circuit that monitors the local output switching condition, and intelligently adjusts its slew rate such that the I/O can switch as fast as it is allowed without jeopardizing noise performance. The second circuit is a PVT-compensation control circuit, which senses process, ...


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Educational Resources on On-chip Pvt Sensing Circuits

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IEEE.tv Videos

Shantanu Chakrabartty - SSCS Chip Chat Podcast, Episode 5
R. Jacob Baker - SSCS Chip Chat Podcast, Episode 4
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
Nanophotonic Devices for Quantum Information Processing: Optical Computing - Carsten Schuck at INC 2019
Episode 2 - Albert Theuwissen - Chip Chat Podcast
Alice Wang - SSCS Chip Chat Podcast, Episode 6
Education for Analog ICs
Multi-Function VCO Chip for Materials Sensing and More - Jens Reinstaedt - RFIC Showcase 2018
Coherent Photonic Architectures: The Missing Link? - Hideo Mabuchi: 2016 International Conference on Rebooting Computing
2017 IEEE Donald O. Pederson Award in Solid-State Circuits: Takao Nishitani and John S. Thompson
On-chip Passive Photonic Reservoir Computing with Integrated Optical Readout - IEEE Rebooting Computing 2017
A Damping Pulse Generator Based on Regenerated Trigger Switch: RFIC Interactive Forum
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
Shanthi Pavan - SSCS Chip Chat Podcast, Episode 3
Towards On-Chip Optical FFTs for Convolutional Neural Networks - IEEE Rebooting Computing 2017
IMS 2014:Flip Chip Assembly for Sub-millimeter Wave Amplifier MMIC on Polyimide Substrate
Critical Update: KeyTalk with Cian O'Mathuna
A Low-Power Fully Integrated 76-81GHz ADPLL for Automotive Applications - Ahmed R. Fridi - RFIC 2019 Showcase
Episode 1 - Gert Cauwenberghs - Chip Chat Podcast
Physical Restraints on Quantum Circuits - IEEE Rebooting Computing 2017

IEEE-USA E-Books

  • CMOS mixed signal SoC for low-side current sensing

    A switched capacitor low-side current sensing signal conditioning circuit with high dynamic range is demonstrated in AMS 0.35 μm, 3.3 V CMOS process. The design incorporates a Switched Capacitor Programmable Gain Amplifier (SC-PGA) and multi-bit second order ΔΣ-ADC. The switched capacitor eliminates the need for explicit level-shifting and chopping circuits thus facilitating sensing of input signal with zero common-mode. Both PGA and ΔΣ-ADC operate at 2 MHz sampling rate. The signal bandwidth (BW) for the design is 1 KHz with an Over Sampling Ratio(OSR) of 1024. The ΔΣ-ADC when tested stand-alone achieves an SNDR of 84 dB over a signal band of 1 kHz while consuming 2.14 mW of power thus achieving a Schreir's FoM of 163 dB. The complete signal-chain that includes the SC-PGA and ΔΣ-ADC achieves an SNDR of 73 dB while consuming 4.78 mW of power thus realizing a low-power and very sensitive low-side current sensing circuit that can sense currents from 1500 A down to 1 A across a 100 μΩ shunt resistor resulting in a voltage sensitivity of 100 μV and step-size of 36 μV.

  • On-chip PVT compensation technology for adaptive voltage scaling control in computer power management application

    Power efficiency has become a major issue in computer Power Management Unit (PMU) as modern Integral Circuit (IC) is scaling toward smaller feature size. In high-performance computing applications, PMU electronics suffer from extensive Process-Voltage-Temperature (PVT) variation since high-level integration has exceeded physical limit of semiconductor material. This paper provides an overview of adaptive powerperformance management with emphasis on design optimization to bound dynamic losses. The challenge on mitigating the PVT influence in a current-mode control PMU has been discussed, with emphasis on key parameters of threshold voltage and on-state resistance. A PVT compensation solution is henceforth introduced which implements on-chip sensing technology to represent the driver performance. High accurate current sensing is achieved. Featuring a synchronous DC-DC step-down voltage regulator as example, simulation results show 43% reduction on power consumption is achieved by static compensation. In addition, an Adaptive Voltage Scaling (AVS) strategy is described which is configured to alter the gate driver to optimize the power efficiency over whole operation range.

  • A low power, moderate accurate, single stage driver circuit for on-chip voltage regulator

    A new single stage driver circuit with improved load regulation is proposed for an on-chip voltage regulator. A load sensing circuit for low static power under light load conditions is also proposed. Lastly, a new coupling technique is proposed for improved transient and stability performance of the regulator

  • Low cost low power POR circuit for low voltage sensing using adaptive bulk biasing

    Many VLSI application system operate I/O supplies and core supplies and follow a predefined power up sequence. In this paper, a technique is presented to design low cost low power on reset circuit targeting low power applications. For designs operating on two supply (IOs etc.), most of the application requires power supply sequence free implementation and in order to do so, they need a signal to shut off the consumption and provide a fixed logic. The proposed circuitry helps in achieving the goal with very small consumption and area (2200 pm2). This circuit consumes maximum 3.2 μA static current in any state. The current consumption of proposed circuit is very low as compared to bandgap based POR circuit and very faster than inverter based conventional POR circuit. The proposed circuit works accurately for both ramp up and ramp down of power supply with varied possible transition times ranging from 10us to 10ms. Due to very low static current consumption and very fast response we can use this circuit in ultra-low power applications like IoT, imaging, sensing, biomedical and space. The proposed strategy has been presented with an implementation in 28nm CMOS FD-SOI technology and verified.

  • Output buffer with self-adjusting slew rate and on-chip compensation

    In this paper, two circuits are proposed to effectively control IC noise. The first circuit is a modified I/O circuit that monitors the local output switching condition, and intelligently adjusts its slew rate such that the I/O can switch as fast as it is allowed without jeopardizing noise performance. The second circuit is a PVT-compensation control circuit, which senses process, voltage, and temperature variations, and compensates the I/O circuit's current drive accordingly. This feature makes the I/O circuits more robust under a range of environmental stresses. From analyses and simulations, the proposed I/O and PVT-compensation control circuits demonstrate robustness in terms of IC noise control. They control IC noise to less than 10% variation between single and multiple output switchings as compared to a conventional I/O circuit with 56% variation.

  • A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application

    Accurate current and voltage measurements are essential for estimating the state of charge of an automotive battery. Typically, circuits are designed to measure low-side current of lead-acid battery. These circuits, however, require a precision reference voltage across a temperature range. In this paper, a design of an on-chip precision bandgap reference with a digitally calibrated technique is described. The bandgap is trimmed for temperature and magnitude and is calibrated digitally. Experimental results show that a maximum of 0.06% variation in the bandgap output for a temperature range of -40 °C-100 °C at a power supply voltage of 3.3 V is achieved. The integrated circuit is fabricated in 0.35-μm standard CMOS technology and occupies an area of 0.23 mm2.

  • An on-chip voltage regulator with improved load regulation and light load power efficiency

    A new single stage driver circuit with improved load regulation is proposed for an on-chip voltage regulator. The improved load regulation was obtained by adding a load dependent extra current at an appropriate node of the driver circuit. Further, a load sensing circuit is proposed for improving the light load power efficiency of the on-chip voltage regulator. The circuit is implemented in 0.11 /spl mu/m CMOS technology. The on-chip voltage regulator generates 1.2V from 1.8V supply. The on-chip voltage regulator load current varies from 0mA to 960mA. Simulation results showed extra offset of 268mV for single stage driver without additional circuitry, where as with additional circuitry the offset was found to be 97mV, when the load current was varied from max to min load. Results also showed up 60% power savings under light load conditions, with only 32% power increase under max load conditions. The proposed circuit is particularly useful for applications with large dynamic range of load current.

  • Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit

    We design a low-voltage high-sensitivity random-process-variations sensor using an on-chip calibration circuit for improved accuracy. The sensor features a replica-biasing circuit that compensates global PVT variations and maintains sensitivity for robust operation. Measurement results from 90 nm test hip demonstrate the effectiveness of the sensor.

  • Fine-grained on-line power monitoring for soft microprocessor based system-on-chip

    Today's CMOS technologies allow larger circuit designs to fit on a single chip. However, this advantage comes at a high price of increased process- voltage-temperature (PVT) variations. FPGAs and their designs are no exceptions to such variations. In fact, the same bit file loaded into two different FPGAs of the same model can produce a significant difference in power and thermal characteristics due to variations that exist within the chip. Since it is increasingly difficult to control physical variations through manufacturing tasks, there is a need for practical ways to sense chip variations to provide a way for circuit designers to compensate or avoid its negative effects. One of the most critical aspects of such variation is power. Therefore, we developed and demonstrated a high accuracy on-chip on-line Energy-per-Component (EPC) measurement technology on Xilinx FPGAs since 2011. However, we found that the hardware overhead associated with such method limited the use of the technology. Therefore, our follow-up work in Energy- per-Operation (EPO) on Spartan FPGA with OpenRISC SoC produced an equally accurate power monitoring technology with drastically lower hardware overhead. While this method made our technology more practical for SoC designs on FPGAs, it did not produce component level power dissipation data that previous EPC method provided. Therefore, we extend this prior work with a new algorithm to extract EPC values from EPO result. Despite the lower hardware overhead, this change ended up improving the accuracy of the power result by unraveling the instruction-level abstraction into component-level energy consumption.

  • Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design

    We propose a low area overhead and power-efficient asynchronous-logic quasi- delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) approach with quad- rail (i.e., 1-of-4) data encoding. The proposed quad-rail SAHB approach is targeted for area- and energy-efficient asynchronous network-on-chip (ANoC) router designs. There are three main features in the proposed quad-rail SAHB approach. First, the quad-rail SAHB is designed to use four wires for selecting four ANoC router directions, hence reducing the number of transistors and area overhead. Second, the quad-rail SAHB switches only one out of four wires for 2-bit data propagation, hence reducing the number of transistor switchings and dynamic power dissipation. Third, the quad-rail SAHB abides by QDI rules, hence the designed ANoC router features high operational robustness toward process-voltage-temperature (PVT) variations. Based on the 65-nm CMOS process, we use the proposed quad-rail SAHB to implement and prototype an 18-bit ANoC router design. When benchmarked against the dual-rail counterpart, the proposed quad-rail SAHB ANoC router features 32% smaller area and dissipates 50% lower energy under the same excellent operational robustness toward PVT variations. When compared to the other reported ANoC routers, our proposed quad-rail SAHB ANoC router is one of the high operational robustness, smallest area, and most energy-efficient designs.



Standards related to On-chip Pvt Sensing Circuits

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(Replaced) IEEE Standard VHDL Language Reference Manual

his standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.


IEEE Application Guide for Low-Voltage AC Power Circuit Breakers Applied with Separately-Mounted Current-Limiting Fuses

This guide applies to low-voltage ac power circuit breakers of the 635 V maximum voltage class with separately-mounted current-limiting fuses for use on ac circuits with available short-circuit currents of 200 000 A (rms symmetrical) or less. Low-voltage ac fused power circuit breakers and combinations of fuses and molded-case circuit breakers are not covered by this guide. This guide sets ...


IEEE Draft Standard for Information technology--Telecommunications and information exchange between systems--Local and metropolitan area networks--Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Amendment: Physical Layer and Management Parameters for Serial 40 Gb/s Ethernet Operation Over Single Mode Fiber

The scope of this project is to add a single-mode fiber Physical Medium Dependent (PMD) option for serial 40 Gb/s operation by specifying additions to, and appropriate modifications of, IEEE Std 802.3-2008 as amended by the IEEE P802.3ba project (and any other approved amendment or corrigendum).


IEEE Draft Standard for Information technology--Telecommunications and information exchange between systems--Local and metropolitan area networks--Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer SpecificationsAmendment: Media Access Control (MAC) service interface and management parameters to support time synchronization protocols

Amend IEEE Std 802.3-2008 to extend the Media Access Control service interface and add management parameters to provide support for the IEEE 802.1AS time synchronization protocol.


IEEE Guide for Control of Small Hydroelectric Power Plants


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Jobs related to On-chip Pvt Sensing Circuits

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