On-chip Power Conversion
158 resources related to On-chip Power Conversion
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Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies
The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE
ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.
APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics
2020 IEEE Energy Conversion Congress and Exposition (ECCE)
IEEE-ECCE 2020 brings together practicing engineers, researchers, entrepreneurs and other professionals for interactive and multi-disciplinary discussions on the latest advances in energy conversion technologies. The Conference provides a unique platform for promoting your organization.
The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.
Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission
The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...
2011 IEEE Hot Chips 23 Symposium (HCS), 2011
This article consists of a collection of slides from the author's conference presentation on the deployment of integrated inductors with magnetic materials for on-chip power conversion. Some of the specific topics discussed include: the special features and processing capabilities of DC voltage converters; the properties of magnetic materials; and key features and processing capabilities of inductors.
2016 IEEE International Electron Devices Meeting (IEDM), 2016
We experimentally demonstrate high performance magnetic inductors with Q as high as 17 in the frequency range of 50-250 MHz. These inductors meet target requirements for >90% efficient on-chip power converters. Physics-based models were used to understand magnetic losses, design novel magnetic stacks and innovative processes to achieve high Q.
IEEE Transactions on Magnetics, 2012
Saturation in thin film coupled magnetic inductors was measured as a function of dc current in both windings. A simple mathematical model was created to approximate the inductor saturation level in the presence of the two currents. The model was compared both to FEM calculations of saturation in a linear model and to the experimental findings. Using the mathematical model, ...
2014 IEEE International Electron Devices Meeting, 2014
Air-core slab inductors with specially designed current return paths are proposed to achieve the ultra-high Q required for on-chip power delivery and management at >90% efficiency. Uniquely optimized for buck converter circuits, this CMOS-compatible structure avoids the challenges of thin-film magnetics. Q~25-30 at 200-300MHz is experimentally demonstrated.
IEEE Transactions on Magnetics, 2013
Successful implementation of on-chip power conversion using ferromagnetic inductors requires both high power efficiency and high power density. The theoretical limits to power density and efficiency possible with thin film ferromagnetic inductors in a buck converter topology with and without coupling are explored. Power density can be related to energy density of the inductor, while efficiency can be related to ...
Conversion of Artificial Recurrent Neural Networks to Spiking Neural Networks for Low-power Neuromorphic Hardware - Emre Neftci: 2016 International Conference on Rebooting Computing
Critical Update: KeyTalk with Cian O'Mathuna
Challenges Associated with VHF Power Conversion - Anthony Sagneri at APEC 2016
ECCE Plenary: Pedro Ray, part 2
IEEE WEBINAR SERIES-March 5th, 2014: GaN Crushing Silicon...and Let Me Tell You How
GaN Transistors -- Crushing Silicon in Wireless Energy Transfer
ECCE Plenary: Richard K. Williams, part 1
Patrizio Vinciarelli, Newell Award: APEC 2019
A 28GHz CMOS Direct Conversion Transceiver with Packaged Antenna Arrays for 5G Cellular Systems: RFIC Industry Showcase 2017
KeyTalk with Conor Quinn: Empowering the Electronics Industry - A Power Technology Roadmap - APEC 2017
The Future of Power Electronics Design - Michael Harrison at APEC 2016
ECCE Plenary: Lennart Jonsson, part 2
Shantanu Chakrabartty - SSCS Chip Chat Podcast, Episode 5
ECCE Plenary: Lennart Jonsson, part 1
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
KeyTalk with Ljubisa Stevanovic: From SiC MOSFET Devices to MW-scale Power Converters - APEC 2017
Design of Monolithic Silicon-Based Envelope-Tracking Power Amplifiers for Broadband Wireless Applications
A 200um x 200um x 100um, 63nW, 2.4GHz Injectable Fully-Monolithic Wireless BioSensing System: RFIC Industry Showcase 2017
Does Power Efficiency Improve with Consolidation in the Semiconductor Industry? - Hans Stork, APEC 2018
This paper introduces the Dual-Frequency Single-Inductor Multiple-Output (DF- SIMO) power converter topology as a cost-effective and power-efficient method for implementing a large number of on-chip power supplies (i.e. on-chip power grids) in nanometer CMOS System-on-Chip (SoCs). The proposed topology decouples the rate of energy conversion at the input of the converter from the rate of energy distribution to the outputs, and thus, output bandwidth and dynamic behavior become no longer limited by the switching frequency at the input side. Low switching frequency at the input side can be used to preserve high power conversion efficiency, while high switching frequency for energy distribution at the output side can be used to reduce the output capacitors to integrate-able levels where they can be implemented on-chip. This limits off- chip components to a single inductor and reduces the package pin count, which results into a lower overall cost per power supply. Dynamic performance is also improved due to the high frequency energy distribution. A 5-output DF- SIMO buck converter design in 45nm CMOS is introduced as an application to the proposed concept.
To provide a high quality power delivery system, the power needs to be regulated on-chip with ultra-small locally distributed power efficient converters. Historically, power efficient switching converters require large physical area, while compact linear power supplies exhibit high power conversion losses, which are not ideal for on-chip integration. To exploit the advantages of existing power supplies, a heterogeneous power delivery system is proposed. The power efficiency of the system is shown to be a strong function of the on-chip distribution of the power supplies. The optimal power distribution system with minimum power losses is determined by exhaustively comparing the power efficiency for all possible power supply topologies. A heterogeneous system with ten on-chip voltage domains and an optimal power distribution network has been evaluated, demonstrating up to 93% power efficiency. A power efficient clustering of the on-chip power supplies with linear computational complexity is also proposed. Heterogeneous power delivery systems with up to 100 on-chip voltage domains have been evaluated with power supplies distributed with linear computational complexity. A maximum 1.5% drop in power efficiency from the optimal solution has been observed, yielding a near optimal and high fidelity power supply distribution system.
This paper describes a digital controller for high-frequency single-phase power factor correction rectifiers (PFC) that is suitable for on-chip implementation. To achieve high switching frequency, fast dynamic response, and implementation with a small number of logic gates, the designs of basic functional blocks are optimized. In the outer voltage loop a windowed based analog-to-digital converter (ADC) with adjustable quantization steps is used, to achieve fast dynamic response. The complexity of the current loop realization is significantly reduced through the utilization of a floating reference created by a Sigma-Delta modulator and another windowed based ADC. In addition, a segmented ring-oscillator based digital pulse-width modulator (DPWM) is used to eliminate the need for a high frequency external clock and reduce the overall size of the system. The effectiveness of this digital architecture is demonstrated on a 200 kHz, 300 W boost-based PFC experimental prototype.
The paper introduces the concept of power supply on chip (PwrSoC) which will enable the development of next generation, functionally integrated, power management platforms with applications in dc-dc conversion, gate drives, isolated power transmission and ultimately, high granularity, on-chip, power management for mixed-signal, SOC chips. PwrSoC will integrate power passives with the power management IC, in a 3D stacked or monolithic form factor, thereby delivering the performance of a high efficiency dc-dc converter within the footprint of a low efficiency linear regulator. A central element of the PwrSoC concept is the fabrication of power micro-magnetics on silicon to deliver micro-inductors and micro-transformers. The paper details the magnetics on silicon process which combines thin film magnetic core technology with electroplated copper conductors. Measured data for micro-inductors show inductance operation up to 20MHz, footprints down to 0.5mm2, efficiencies up to 93% and dc current carrying capability up to 600mA. Measurements on micro- transformers show voltage gain of approximately -1dB at between 10MHz and 30 MHz.
A low-power, high-speed on-chip compression and reconstruction technique is proposed in this paper. It takes the advantage of correlation between the consecutive pixels and reduces the total number of pixels to be read. The discarded pixels are interpolated on-chip using the proposed interpolation circuit. This reduces the total number of A/D conversions and hence results in power saving. The algorithm is verified for standard Lena image and about 5 dB better PSNR is observed for 20%- 90% compression, as compared to the existing techniques. Moreover, a promising performance is achieved on thermal image applications. The circuit is designed and simulated in AMS 350 nm OPTO process. For 57% compression, about 45% power saving in readout of the image sensor is observed.
Saturation in thin film coupled magnetic inductors was measured as a function of dc current in both windings. A simple mathematical model was created to approximate the inductor saturation level in the presence of the two currents. The model was compared both to FEM calculations of saturation in a linear model and to the experimental findings. Using the mathematical model, an expression for the maximum dc current and maximum flux levels in the yokes was derived for a two phase coupled buck converter, as a function of coupling.
In this paper, which based on the National High-tech R&D Program of China " design, monitoring, management and protection technology for large-capacity storage system ". it is described that design requirement of the cascaded H-bridge power conversion system, main circuit topology and power unit topology including the way of selecting and confirming the method of the modulation. Key parameters are discussed and power losses are analyzed. Besides, a prototype is built to verify the functions of cascaded H-bridge power conversion system. A series of experiments show that the power control can be achieved flexibly and the SOC balance within one phase and among phases can work with a low harmonic.
The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators are used to adjust the local power supply. The smart power-switch allows us to keep the global power network unchanged. It offers an integrated standby mode and has a fast dynamic response, i.e. low transition times between voltage steps at the cost of the reduced power conversion efficiency when compared to complex DC-DC converters.
Tradeoff between power efficiency and transient performance usually comes out during the design consideration of a power module. A configurable power supplying implementation named as the power cloud system (PCS) is proposed to handle different load conditions for simultaneously improving the power efficiency and the transient response in order to meet the system-on-chip (SoC) requirements. At heavy loads, the switching regulator takes over the energy delivery scheme in the PCS with the fast transient technique. An auxiliary power unit, which activates hybrid operation in both medium and light loads, can realize the low-dropout (LDO) regulator to provide a supplementary energy immediately in transient duration and be the high-side power switches of the switching regulator to minimize the power loss. Besides, owing to its low quiescent current of an LDO regulator, it can directly operate under the ultralight-load condition. Therefore, the satisfactory power conversion efficiency and the load transient response can be derived over a wide load range, which will certainly meet the power requirement for different operated functions in the SoC. The chip was fabricated by a 0.25-μm CMOS process, and the experimental results show the improvements of 56% transient dip voltage and 25% transient recovery time in hybrid operation, as well as a peak efficiency of 94%.
This paper presents ultra low power hybrid energy harvesting start-up circuit for 1V , implemented in a standard 0.18 μm CMOS technology. It consists of solar and RF energy harvesters, capable to harvest ambient solar and RF sources respectively. The start-up circuit enables operation of the system even in the absence of any one of these ambient energy sources. The integration of solar and RF on a common platform provides improved charging time in crucial start-up phase. In general, to charge the super capacitor (Cstartup=100pF) to 1V , the solar energy harvester alone (with minimum input voltage of 317mV ) will take a charging time of 542.3μs. With the addition of RF interface, the charging time is drastically reduced to 86.8μs, for -26dBm input power level, at 953MHz providing a 83.9% reduction in start-up time. The start-up circuit delivers output power of 7.4μW with an efficiency of 68.5% for the combined solar and RF input at 317mV and -20dBm respectively.