Networks On Chip
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Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies
The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.
ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.
ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.
The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.
The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...
2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2014
Networks-on-Chip (NoCs) offer a scalable means of on-chip communication for future many-core chips. This work explores NoC router microarchitectures which leverage traffic pattern biases and imbalances to reduce latency and improve throughput. It introduces STORM, a new, low-latency, fair, highth-roughput NoC router design, customized for the traffic seen in a two-dimensional mesh network employing dimension-order routing. Compared to a baseline ...
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008
Through low-level simulation and analysis, we find that the virtual channel allocator (VA) consumes large area and power while it is not critical in the performances of a NoC. Thus, it is possible to reduce the costs of VA with only a small penalty in network performances. This paper proposes two low-cost VA architectures: look-ahead VA and unfair VA. Compared ...
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008
A network on chip (NoC) with end-to-end flow control is modelled by a cyclo- static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable ...
IEEE Transactions on Computers, 2013
The trend toward integrated many-core architectures makes the network-on-chip (NoC) technology, the on-chip communication infrastructure of choice. However, and as opposed to a simple bus, due to its distributed and complex nature in terms of topology, wire size, routing algorithm, and so on, the timing behavior and thus performance of the infrastructure is difficult to predict. Therefore, one of the ...
2012 Third International Conference on Intelligent Systems Modelling and Simulation, 2012
The Control system algorithms implementation in Networks-on-Chip (NoC) is the best way to address the various issues like power consumption, congestion control, and data packet loss. In this paper, we present the modern control system mapped on NoC. The concept of on chip implementation of Networked Control Systems (NCS) started to grow because of its potential in various applications, it ...
On-chip Passive Photonic Reservoir Computing with Integrated Optical Readout - IEEE Rebooting Computing 2017
IMS 2014:Flip Chip Assembly for Sub-millimeter Wave Amplifier MMIC on Polyimide Substrate
Coherent Photonic Architectures: The Missing Link? - Hideo Mabuchi: 2016 International Conference on Rebooting Computing
2006 IEEE Honors Ceremony
Conversion of Artificial Recurrent Neural Networks to Spiking Neural Networks for Low-power Neuromorphic Hardware - Emre Neftci: 2016 International Conference on Rebooting Computing
Critical Update: KeyTalk with Cian O'Mathuna
Q-Band CMOS Transmitter System-on-Chip - Tim Larocca - RFIC Showcase 2018
Q&A: John Smee & Mikael Hook - B5GS 2019
IMS MicroApps: Single Chip LNA on 0.25um SOS for SKA Midband Receiver
Shantanu Chakrabartty - SSCS Chip Chat Podcast, Episode 5
Useful Quantum Computing - Pete Shadbolt - ICRC San Mateo, 2019
R. Jacob Baker - SSCS Chip Chat Podcast, Episode 4
Brooklyn 5G Summit 2014: Erik Starkloff on Platform Approach to Design
IEEE WIE- TryEngineering Ship the Chip
Panel: Future of 5G - Rel-16 to Rel-18 - B5GS 2019
2017 IEEE Donald O. Pederson Award in Solid-State Circuits: Takao Nishitani and John S. Thompson
A 200um x 200um x 100um, 63nW, 2.4GHz Injectable Fully-Monolithic Wireless BioSensing System: RFIC Industry Showcase 2017
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
A 10-40GHz Frequency Quadrupler Source with Switchable Bandpass Filters and >30dBc Harmonic Rejection: RFIC Interactive Forum 2017
Networks-on-Chip (NoCs) offer a scalable means of on-chip communication for future many-core chips. This work explores NoC router microarchitectures which leverage traffic pattern biases and imbalances to reduce latency and improve throughput. It introduces STORM, a new, low-latency, fair, highth-roughput NoC router design, customized for the traffic seen in a two-dimensional mesh network employing dimension-order routing. Compared to a baseline NoC router with equivalent buffer resources, STORM offers single cycle operation and reduced cycle time (17% less than the baseline on 45nm CMOS). This design yields a higher overall network saturation throughput (13% higher than the baseline) in an 8x8 2D mesh network for uniform random traffic. STORM also reduces packet latencies under realistic workloads by 36% on average.
Through low-level simulation and analysis, we find that the virtual channel allocator (VA) consumes large area and power while it is not critical in the performances of a NoC. Thus, it is possible to reduce the costs of VA with only a small penalty in network performances. This paper proposes two low-cost VA architectures: look-ahead VA and unfair VA. Compared with a general VA, the look- ahead VA reduces the number of both input VC arbiters and output VC arbiters while the unfair VA decreases the size of the output VC arbiters. Our experiments based on UMC 130 nm SP library show that the two architectures jointly save area cost by 70.95% and power consumption by 76.21% with nearly no adverse effect on network latency and throughput. To the best of our knowledge, it is the first time a VC allocator design is optimized in the context of NoC.
A network on chip (NoC) with end-to-end flow control is modelled by a cyclo- static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.
The trend toward integrated many-core architectures makes the network-on-chip (NoC) technology, the on-chip communication infrastructure of choice. However, and as opposed to a simple bus, due to its distributed and complex nature in terms of topology, wire size, routing algorithm, and so on, the timing behavior and thus performance of the infrastructure is difficult to predict. Therefore, one of the important phases in the NoC design flow is performance evaluation, which is to extract performance metrics to verify whether a specific instance from the NoC design space satisfies the requirements of the entire system. In this sense, reducing the time to obtain the NoC performance and consequently speeding-up the design space exploration is one of the keys that can considerably reduce the design-flow time and cost. In an effort toward this direction, we propose in this paper a novel analytical performance evaluation method that can be used in the earliest stages of the design flow, before using time-consuming simulations. The analytical method is used to evaluate the performance of a general purpose NoC and we show that it can predict the router latency, end-to-end per-flow latency, and network saturation point with an accuracy comparable to a cycle-accurate simulation. To systematically analyze the accuracy of our method compared to the corresponding simulation model, we present also an innovative accuracy analysis method.
The Control system algorithms implementation in Networks-on-Chip (NoC) is the best way to address the various issues like power consumption, congestion control, and data packet loss. In this paper, we present the modern control system mapped on NoC. The concept of on chip implementation of Networked Control Systems (NCS) started to grow because of its potential in various applications, it also provided many challenges for researchers to achieve reliable and efficient control. Moreover, the NCS area has been researched for decades and has given rise to many important research topics. Till date NCS has been implemented on World Wide Web. This architecture plays a pivotal role in real time applications like missile control system, robot trajectory, and satellite vehicle orbital trajectory control system.
Error control is imperative for reliable Networks-on-Chip (NoCs) design. In this demo session, we will present a CAD tool-a flexible and parallel NoC simulator. Our simulator evaluates the impact of different error control mechanisms on NoC performance and energy consumption in various noise and traffic injection scenarios. Our message passing interface language-based simulator can be executed on multiprocessors or server clusters. Multiple built-in blocks provide flexibility to evaluate different error control methods.
On-chip wireless optical communications among distant cores in chip multiprocessors can lead to a completely new approach to the limits of current on-chip communication. In fact, using wireless connections mitigates the problems related to the design and the fabrication of hugely complex switching fabrics, where long paths suffer of crosstalk and loss issues. We investigate the possibility of integrating plasmonic nanoantennas and silicon waveguides to allow the compatibility with optical networks and devices. In particular, we report the numerical analysis of a plasmonic Vivaldi antenna coupled to a silicon waveguide. The design criteria and the radiation characteristics are described.
Networks-on-Chip (NoC) has been applied widely in Chip Multi-processors (CMPs). With the development of multi processors systems, multicast communications have been commonly used in these systems. Current multicast algorithms may cause deadlock and suffer from long latency and low throughput. In this paper, we proposed a new multicast algorithm for mesh-based on-chip networks. This new multicast routing method reduces the latency and increases the saturation point. This routing scheme can dynamically make routing decisions based on the network conditions and the distribution of destination nodes. The simulation result, implemented under OPNET, shows that the saturation point of the proposed algorithm is higher than the efficient partition-based routing scheme LADPM . The latency of our routing algorithm is about 21% and 42% smaller than LADPM when the number of the destination nodes is 8 and 4 respectively under high injection rates.
Aèsiraci-Networks-on-Chip are vulnerable to a variety of manufacturing and design factors making them susceptible to disparate faults that cause corrupted message transfer or even catastrophic system failures, due to the central position of the NoC in the system. Therefore, a NoC system should be fault-tolerant to transient malfunctions or permanent physical damages. The terminology of fault tolerant relates to a design capable to continue its operation, probably at a lower efficiency level, instead of failing utterly, when some part of the system fails. This abstract analyzes the main concept of my dissertation witch is the design of a systematic methodology for fault tolerant routing in 2D and 3D NoC, that promises to provide sufficient fault coverage with reasonable overhead in terms of hardware redundancy and performance (e.g. delay/power) degradation, given the designer's requirements and constraints.
Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in Chip Multiprocessors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and in various parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at the hardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs, each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore the efficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose the Minimal and Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show that an advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the network until all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsets and the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performance improvement across all workloads while performance can be further improved by utilizing the MAR algorithm. Nineteen percent average and 42 percent maximum latency reduction are obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.
IEEE Draft Standard for Information technology--Telecommunications and information exchange between systems--Local and metropolitan area networks--Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Amendment: Physical Layer and Management Parameters for Serial 40 Gb/s Ethernet Operation Over Single Mode Fiber
The scope of this project is to add a single-mode fiber Physical Medium Dependent (PMD) option for serial 40 Gb/s operation by specifying additions to, and appropriate modifications of, IEEE Std 802.3-2008 as amended by the IEEE P802.3ba project (and any other approved amendment or corrigendum).
This standard contains the Management Information Base (MIB) module specifications for IEEE Std 802.3, also known as Ethernet. It includes the Structure of Management Information Version 2 (SMIv2) MIB module specifications formerly produced and published by the Internet Engineering Task Force (IETF), and the Guidelines for the Definition of Managed Objects (GDMO) MIB modules formerly specified within IEEE Std 802.3, ...
This standard amends the IEEE 802.16 WirelessMAN-OFDMA specification to provide an advanced air interface for operation in licensed bands. It meets the cellular layer requirements of IMT-Advanced next generation mobile networks. This amendment provides continuing support for legacy WirelessMAN-OFDMA equipment.
This standard specifies unique per-device identifiers (DevID) and the management and cryptographic binding of a device to its identifiers, the relationship between an initially installed identity and subsequent locally significant identities, and interfaces and methods for use of DevIDs with existing and new provisioning and authentication protocols.