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Xplore Articles related to Sram Cells

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A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019

The Static Random Access Memory (SRAM) has huge impact on the overall power consumption of any digital design. SRAM consumes a significant amount of power in the idle state. Therefore, the leakage power is one of the most critical metrics in SRAM designs. This paper evaluates the standby leakage power of GNRFET based 6T SRAM bitcell and compared to 10nm ...


Compact modeling of Random Telegraph Noise in nanoscale MOSFETs and impacts on digital circuits

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014

The complexity of Random Telegraph Noise (RTN) under digital circuit operations makes it difficult to predict its impacts without accurate modeling and simulation. However, properly integrating RTN into circuit simulation is challenging due to its stochastic nature. In this paper, RTN is comprehensively modeled and embedded into BSIM. A circuit simulation methodology based on industry-standard EDA tools is proposed, resolving ...


N-Curve Analysis of Low power SRAM Cell

2018 Second International Conference on Inventive Communication and Computational Technologies (ICICCT), 2018

In this paper, a low power SRAM cell is proposed, whose leakage power is almost negligible compared to that of conventional 6T SRAM cell. All the stability parameters like static voltage noise margin(SVNM), static current noise margin(SINM), write trip voltage (WTV) and write trip current (WTI) are calculated using N-curve analysis. A better write stability is achieved for the proposed ...


A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology

2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), 2016

Data stability, performance and leakage currents are the few important issues of Static Random Access Memory (SRAM) due to scaling down the technology. We revisited these issues by making a comparative study of N-Controlled SRAM cell (NC-SRAM) and PMOS pass transistor SRAM cell (PP-SRAM) with conventional 6T SRAM cell. We observe decrease in Static Noise Margin (SNM) of NC-SRAM and ...


A regression based methodology to estimate SNM for improving yield of 6T SRAM

2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 2016

The stability of SRAM cells in high density ICs during read cycle is an extremely critical performance metric for data retention. A frame work to identify the tradeoff between Yield and Static Noise Margin (SNM) in the region of high sigma tail end distributions is presented in this paper. For developing the framework, the sensitivity of SNM is observed for ...


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IEEE-USA E-Books

  • A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET

    The Static Random Access Memory (SRAM) has huge impact on the overall power consumption of any digital design. SRAM consumes a significant amount of power in the idle state. Therefore, the leakage power is one of the most critical metrics in SRAM designs. This paper evaluates the standby leakage power of GNRFET based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The paper also presents an analysis of the stability and reliability of GNRFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T GNRFET SRAM cell. Simulations were performed in HSPICE and Cadence tools.

  • Compact modeling of Random Telegraph Noise in nanoscale MOSFETs and impacts on digital circuits

    The complexity of Random Telegraph Noise (RTN) under digital circuit operations makes it difficult to predict its impacts without accurate modeling and simulation. However, properly integrating RTN into circuit simulation is challenging due to its stochastic nature. In this paper, RTN is comprehensively modeled and embedded into BSIM. A circuit simulation methodology based on industry-standard EDA tools is proposed, resolving the stochastic property, the AC effects, and the coupling of RTN and circuits that are crucial for accurate predictions of impacts of RTN. Using the compact model and proposed method, impacts of RTN on RO and SRAM are demonstrated, which ascertains their applicability to different type of circuits.

  • N-Curve Analysis of Low power SRAM Cell

    In this paper, a low power SRAM cell is proposed, whose leakage power is almost negligible compared to that of conventional 6T SRAM cell. All the stability parameters like static voltage noise margin(SVNM), static current noise margin(SINM), write trip voltage (WTV) and write trip current (WTI) are calculated using N-curve analysis. A better write stability is achieved for the proposed cell than 6T SRAM cell with a slight reduction in the read stability. The N-curves are plotted under different process corners and different temperatures. The standby power of the 6T SRAM cell and proposed SRAM cell is 6.22nW and 4.23uW respectively. Therefore, for low standby power applications the proposed cell is more suitable. Cadence tools are used for simulation of SRAM cells with gpdk 45-nm technology.

  • A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology

    Data stability, performance and leakage currents are the few important issues of Static Random Access Memory (SRAM) due to scaling down the technology. We revisited these issues by making a comparative study of N-Controlled SRAM cell (NC-SRAM) and PMOS pass transistor SRAM cell (PP-SRAM) with conventional 6T SRAM cell. We observe decrease in Static Noise Margin (SNM) of NC-SRAM and PP- SRAM cells with 6T SRAM cell in hold mode by 60.09% and 0.22% at temperature (T) = 25°C, 63.25% and 3.34% at T = 50°C, 63.82% and 3.37% at T = 100°C respectively. For our transistors sizing we obtain a degradation in write operation of NC-SRAM cell by 7.31% compare to 6T SRAM cell, While it is unchanged in case of PP-SRAM cell. Significant reduction in total leakage power is obtained for NC and PP-SRAM cells compared to 6T SRAM cell by 77.06% and 47.42% at T = 25°C, 76.89% and 48.98% at T = 50°C, 76.87% and 50.94% at T = 100°C respectively, which is due to the gate and sub-threshold leakage currents. We also design a 16 bit memory array of 6T, NC and PP SRAM cells. There is a reduction in total leakage power for 16 bit array of NC and PP-SRAM cells by 69.86 %, 50.75 % respectively compared to the 16 bit array of 6T SRAM cell. All the simulations are performed by Cadence Virtuoso (version IC 6.1.6.500.1) tool using gpdk 45nm CMOS process technology.

  • A regression based methodology to estimate SNM for improving yield of 6T SRAM

    The stability of SRAM cells in high density ICs during read cycle is an extremely critical performance metric for data retention. A frame work to identify the tradeoff between Yield and Static Noise Margin (SNM) in the region of high sigma tail end distributions is presented in this paper. For developing the framework, the sensitivity of SNM is observed for different device variations using Design of Experiments (DoE) method whereas estimation of yield for different targeted SNMs is done using Bivariate Linear (BL) model and Bivariate Nonlinear Quadratic (BNLQ) models. The developed framework demonstrates that for achieving a yield of 99% there is a need to design a memory cell at a cost of 150mV SNM using BL model post silicon. On the other hand at the same cost of 150mV SNM, the yield can be enhanced to 99.5% if BNLQ model is adopted post silicon.

  • A Power and Static Noise Margin Analysis of different SRAM cells at 180nm Technology

    SRAM cell stability and leakage power consumption is one of the primary concern in nanotechnology era. Threshold voltage (Vth) of MOS changes with temperature and thereby leakage power of MOS. We analyze static noise margin (SNM) and leakage power at different Temperature and Power supply for different SRAM cells 6T, 8T, 9T and 10T. Simulations are done on cadence virtuoso tool. The result shows that 9T SRAM cell have better performance, power consumption and static noise margin compared to other three structures. Results shows that 9T SRAM cell has at least 20% less leakage Power with respect to 10T SRAM cell and have 150% increased static noise margin over conventional 6T SRAM cell.

  • Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs

    Dual Rail SRAMs are widely used to enable Dynamic Voltage and Frequency Scaling (DVFS) in SRAMs where array voltage cannot be scaled down. DVFS operating points are limited by maximum differential supported between two supplies of the SRAM. To extend gains of DVFS, we propose a Low Standby Power - Capacitively Coupled Sense Amplifier (LSTP-C2SA) that enables further lowering of periphery supply in Dual Rail SRAMs without leading to SRAM cell instability. We present a design method to optimally size the coupling capacitance in LSTP-C2SAs. Designs with LSTP-C2SA are shown to consume 43% lesser read power in DVFS operation at 0.4V in 28nm UTBB FD-SOI when compared to an implementation with standard latch sense amplifier. Silicon measurements confirm LSTP-C2SA functionality at 0.35V.

  • The Features of Radiation-Hardening-By-Design of Bulk SRAM Cells

    The main circuit design and constructive-topological SRAM cells Radiation- Hardening-By-Design (RHBD) methods applied in 250 ... 90 nm bulk CMOS processes were analyzed. The test chip research results show that an increase of the 6T-memory cell area by 1.5 times can significantly improve the tolerance to all the radiation factors. The CMOS SRAM 4 Mbit, 16 Mbit chips and IP-blocks as part of ASIC were designed and implemented in 250 ... 90 nm bulk CMOS processes using the considered RHBD methods.

  • Efficient multi-bit SRAMs using spatial wavefunction switched (SWS)-FETs

    This paper presents the multiple quantum well channel spatial wavefunction switched FETs (SWS-FETs) configured to implement multi-bit static random access memory (SRAM) cells. A 2-bit SRAM cell consists of two back-to-back connected 4-channel SWS-FETs, where each SWS-FET serves as quaternary inverter. This architecture results in reduction of FET count by 75% and data interconnect density by 50%. The designed 2-bit SRAM cell is simulated using BSIM equivalent channel models (for 25nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS- SRAM technology. Quantum simulations for Si/Ge and InGaAs-based SWS-FETs are also presented.

  • Highly stable subthreshold single-ended 7T SRAM cell

    This article presents a highly stable single-ended 7T (SE-7T) SRAM cell in subthreshold region. Using Monte-Carlo simulations critical design metrics of proposed SE-7T SRAM cells are estimated. Estimated results are compared with that of conventional 6T SRAM cell. The SE-7T SRAM cell offers 2.71× and 2.71× and 8.42 X improvements in Read Access Time (TRA) and Write Access Time (TWA) for write-1 and write-0 respectively. The proposed bit cell also offers 3.28× improvement in read static noise margin (RSNM) and 1.22× higher hold power@ 350 mV.



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