Conferences related to Memory Architectures

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


2020 IEEE International Conference on Multimedia and Expo (ICME)

Multimedia technologies, systems and applications for both research and development of communications, circuits and systems, computer, and signal processing communities.

  • 2019 IEEE International Conference on Multimedia and Expo (ICME)

    speech, audio, image, video, text and new sensor signal processingsignal processing for media integration3D imaging, visualization and animationvirtual reality and augmented realitymulti-modal multimedia computing systems and human-machine interactionmultimedia communications and networkingmedia content analysis and searchmultimedia quality assessmentmultimedia security and content protectionmultimedia applications and servicesmultimedia standards and related issues

  • 2018 IEEE International Conference on Multimedia and Expo (ICME)

    The IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE societies since 2000. It serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities. ICME also features an Exposition of multimedia products and prototypes.

  • 2017 IEEE International Conference on Multimedia and Expo (ICME)

    Topics of interest include, but are not limited to: – Speech, audio, image, video, text and new sensor signal processing – Signal processing for media integration – 3D visualization and animation – 3D imaging and 3DTV – Virtual reality and augmented reality – Multi-modal multimedia computing systems and human-machine interaction – Multimedia communications and networking – Media content analysis – Multimedia quality assessment – Multimedia security and content protection – Multimedia databases and digital libraries – Multimedia applications and services – Multimedia standards and related issues

  • 2016 IEEE International Conference on Multimedia and Expo (ICME)

    Topics of interest include, but are not limited to:- Speech, audio, image, video, text and new sensor signal processing- Signal processing for media integration- 3D visualization and animation- 3D imaging and 3DTV- Virtual reality and augmented reality- Multi-modal multimedia computing systems and human-machine interaction- Multimedia communications and networking- Media content analysis- Multimedia quality assessment- Multimedia security and content protection- Multimedia databases and digital libraries- Multimedia applications and services- Multimedia standards and related issues

  • 2015 IEEE International Conference on Multimedia and Expo (ICME)

    With around 1000 submissions and 500 participants each year, the IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE societies since 2000. It serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2014 IEEE International Conference on Multimedia and Expo (ICME)

    The IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE societies since 2000. It serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications. In 2014, an Exposition of multimedia products, prototypes and animations will be held in conjunction with the conference.Topics of interest include, but are not limited to:

  • 2013 IEEE International Conference on Multimedia and Expo (ICME)

    To promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2012 IEEE International Conference on Multimedia and Expo (ICME)

    IEEE International Conference on Multimedia & Expo (ICME) has been the flagship multimedia conference sponsored by four IEEE Societies. It exchanges the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2011 IEEE International Conference on Multimedia and Expo (ICME)

    Speech, audio, image, video, text processing Signal processing for media integration 3D visualization, animation and virtual reality Multi-modal multimedia computing systems and human-machine interaction Multimedia communications and networking Multimedia security and privacy Multimedia databases and digital libraries Multimedia applications and services Media content analysis and search Hardware and software for multimedia systems Multimedia standards and related issues Multimedia qu

  • 2010 IEEE International Conference on Multimedia and Expo (ICME)

    A flagship multimedia conference sponsored by four IEEE societies, ICME serves as a forum to promote the exchange of the latest advances in multimedia technologies, systems, and applications from both the research and development perspectives of the circuits and systems, communications, computer, and signal processing communities.

  • 2009 IEEE International Conference on Multimedia and Expo (ICME)

    IEEE International Conference on Multimedia & Expo is a major annual international conference with the objective of bringing together researchers, developers, and practitioners from academia and industry working in all areas of multimedia. ICME serves as a forum for the dissemination of state-of-the-art research, development, and implementations of multimedia systems, technologies and applications.

  • 2008 IEEE International Conference on Multimedia and Expo (ICME)

    IEEE International Conference on Multimedia & Expo is a major annual international conference with the objective of bringing together researchers, developers, and practitioners from academia and industry working in all areas of multimedia. ICME serves as a forum for the dissemination of state-of-the-art research, development, and implementations of multimedia systems, technologies and applications.

  • 2007 IEEE International Conference on Multimedia and Expo (ICME)

  • 2006 IEEE International Conference on Multimedia and Expo (ICME)

  • 2005 IEEE International Conference on Multimedia and Expo (ICME)

  • 2004 IEEE International Conference on Multimedia and Expo (ICME)

  • 2003 IEEE International Conference on Multimedia and Expo (ICME)

  • 2002 IEEE International Conference on Multimedia and Expo (ICME)

  • 2001 IEEE International Conference on Multimedia and Expo (ICME)

  • 2000 IEEE International Conference on Multimedia and Expo (ICME)


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


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Periodicals related to Memory Architectures

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


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Most published Xplore authors for Memory Architectures

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Xplore Articles related to Memory Architectures

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Scalable shared-memory architectures. Introduction to the minitrack

1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences, 1994

The single address-space that shared-memory architectures offer simplifies programming, problem partitioning, and dynamic load balancing as compared to other programming models for parallel computing systems such as e.g. Message passing. Unfortunately, as we scale shared-memory architectures to large configurations, the resulting memory system latencies may limit their performance potentials. Finding cost-effective solutions to the memory-system latency issue has become an ...


Generation of distributed logic-memory architectures through high-level synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005

With the increasing cost of on-chip global communication, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout the chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several ...


Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler

2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016

Tools for C/C++ based-hardware development have grown in popularity in recent years. However, the impact of these tools has been limited by their lack of support for integration with vendor IP, external memories, and communication peripherals. In this paper we introduce Tinker, an open-source Board Support Package generator for Altera's OpenCL Compiler. Board Support Packages define memory, communication, and IP ...


Solution of large-scale scattering problems with the multilevel fast multipole algorithm parallelized on distributed-memory architectures

2007 22nd international symposium on computer and information sciences, 2007

We present the solution of large-scale scattering problems involving three- dimensional closed conducting objects with arbitrary shapes. With an efficient parallelization of the multilevel fast multipole algorithm on relatively inexpensive computational platforms using distributed-memory architectures, we perform the iterative solution of integral-equation formulations that are discretized with tens of millions of unknowns. In addition to canonical problems, we also present ...


ES3: Future system and memory architectures: Transformations by technology and applications

2011 IEEE International Solid-State Circuits Conference, 2011

The emergence of new enabling technologies and applications paradigms will likely drive radical changes in the memory architecture of future systems. With multi-core CPU dies sporting embedded DRAM caches, ever-improving NAND flash storage densities for SSD and SCM, and 3D-integration technologies to bring everything together into a single package, possibilities abound for system enhancements throughout the memory hierarchy. At the ...


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Educational Resources on Memory Architectures

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IEEE.tv Videos

A Comparator Design Targeted Towards Neural Net - David Mountain - ICRC San Mateo, 2019
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip - Anirudh Jain - ICRC 2018
Future Computing Systems (FCS) to Support Understanding Capability - Sergey Serebryakov - ICRC San Mateo, 2019
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
What's New in Digital Predistortion
Patrizio Vinciarelli, Newell Award: APEC 2019
IMS 2014 Enabling Technologies and Architectures for 5G Wireless
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
Ted Berger: Far Futures Panel - Technologies for Increasing Human Memory - TTM 2018
Fast solution of linear systems with RRAM - Zhong Sun - ICRC San Mateo, 2019
Impact of Linearity and Write Noise of Analog Resistive Memory: IEEE Rebooting Computing 2017
Non-Volatile Memory Array Based Quantization - Wen Ma - ICRC San Mateo, 2019
Array storing and retrieval
High-Bandwidth Memory Interface Design
5G Virtual RAN Network Architectures - Olufemi Adeyemi - IEEE Sarnoff Symposium, 2019
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth

IEEE-USA E-Books

  • Scalable shared-memory architectures. Introduction to the minitrack

    The single address-space that shared-memory architectures offer simplifies programming, problem partitioning, and dynamic load balancing as compared to other programming models for parallel computing systems such as e.g. Message passing. Unfortunately, as we scale shared-memory architectures to large configurations, the resulting memory system latencies may limit their performance potentials. Finding cost-effective solutions to the memory-system latency issue has become an important research objective and is the main focus of this minitrack. Loosely speaking, scalability for these systems refers to optimizing both the performance and the implementation cost. While it is not meaningful to strictly define the term scalability, it is an important intuitive goal when evaluating new shared-memory architectures.<<ETX>>

  • Generation of distributed logic-memory architectures through high-level synthesis

    With the increasing cost of on-chip global communication, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout the chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. This paper provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse and fine-grained parallelism from data accesses and computations in a synergistic manner. Our methodology selects many possible ways of organizing data and computations, carefully examines the tradeoffs (i.e., communication overheads, synchronization costs, area overheads) in choosing one solution over another, and utilizes conventional HLS techniques for intermediate steps. We have evaluated the proposed framework on several benchmarks by generating register-transfer level (RTL) implementations using an existing commercial HLS tool with and without our enhancements, and by subjecting the resulting RTL circuits to logic synthesis and layout. The results show that circuits designed as distributed logic-memory architectures using our framework achieve significant (up to 5.3/spl times/, average of 3.5/spl times/) performance improvements over well-optimized conventional designs with small area overheads (up to 19.3%, 15.1% on average). At the same time, the reduction in the energy-delay product is by an average of 5.9/spl times/ (up to 11.0/spl times/).

  • Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler

    Tools for C/C++ based-hardware development have grown in popularity in recent years. However, the impact of these tools has been limited by their lack of support for integration with vendor IP, external memories, and communication peripherals. In this paper we introduce Tinker, an open-source Board Support Package generator for Altera's OpenCL Compiler. Board Support Packages define memory, communication, and IP ports for easy integration with high level synthesis cores. Tinker abstracts the low-level hardware details of hardware development when creating board support packages and greatly increases the flexibility of OpenCL development. Tinker currently generates custom memory architectures from user specifications. We use our tool to generate a variety of architectures and apply them to two application kernels.

  • Solution of large-scale scattering problems with the multilevel fast multipole algorithm parallelized on distributed-memory architectures

    We present the solution of large-scale scattering problems involving three- dimensional closed conducting objects with arbitrary shapes. With an efficient parallelization of the multilevel fast multipole algorithm on relatively inexpensive computational platforms using distributed-memory architectures, we perform the iterative solution of integral-equation formulations that are discretized with tens of millions of unknowns. In addition to canonical problems, we also present the solution of real-life problems involving complicated targets with large dimensions.

  • ES3: Future system and memory architectures: Transformations by technology and applications

    The emergence of new enabling technologies and applications paradigms will likely drive radical changes in the memory architecture of future systems. With multi-core CPU dies sporting embedded DRAM caches, ever-improving NAND flash storage densities for SSD and SCM, and 3D-integration technologies to bring everything together into a single package, possibilities abound for system enhancements throughout the memory hierarchy. At the same time, applications needs are rapidly evolving as the world shifts from a product- centric economy to a service- and experience-oriented economy focused on hardware such as smartphones, set-top boxes, and 3D digital TV. This evening session will discuss future system and memory architectures from perspectives spanning the 3 C's: computing, consumer electronics, and communications - considering both what new technology might offer and what new applications might need.

  • A design methodology of buffer-memory architectures for FFT computation

    Memory-based architectures have received great attention for single-chip implementation of the fast Fourier transform (FFT). Basically, they can be roughly categorized as single-memory design, dual-memory design, and buffer- memory design. Among them, the buffer-memory design can balance the trade-off between memory size and control circuit complexity. In this paper, we present a design methodology of buffer-memory architectures for the radix-2 decimation-in-frequency FFT algorithm that can effectively reduce the needed memory. As compared to previous related works, the designs derived from the proposed methodology can reach the same throughput performance with a smaller memory size. These designs are rather attractive for long-length FFT applications, such as very-high-rate digital subscriber lines and digital video broadcasting.

  • An efficient load balancing method for multi-core systems with asymmetric memory architectures

    As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program in a distributed fashion on an asymmetric memory architecture effectively is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade- off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods.

  • Optimization of Checkpoints and Execution Model for an Implementation of OpenMP on Distributed Memory Architectures

    CAPE (Checkpointing-Aide Parallel Execution) is an approach tried to port OpenMP programs on distributed memory architectures like Cluster, Grid or Cloud systems. It provides a set of prototypes and functions to translate automatically and execute OpenMP program on distributed memory systems based on the checkpointing techniques. This solution has shown that it has achieved high performance and complete compatibility with OpenMP. However, it is in research and development stage, so there are many functions that need to be added, some techniques and models need to be improved. This paper presents approaches and techniques that have been applied and will be applied to optimize checkpoints and execution model of CAPE.

  • Automatic scheduling for cache only memory architectures

    For parallel and distributed systems to gain more acceptance than they have to date, they will need to be scalable, affordable-but most importantly, they must be made as easy to program as sequential systems. Ideally, we would like to be able to take programs written in conventional languages and recompile them for parallel architectures, thus freeing the programmer from all additional effort above and beyond that necessary to program a conventional computer. This in turn implies that either the compiler, the hardware, or both, must address the fundamental issue of distribution. This problem is two fold: both data and computation must somehow be distributed. The paper attempts to bring data distribution concepts from cache only memory architectures together with scheduling concepts from multithreaded architectures, in order to arrive at one unified, simplified, cohesive abstract model of computation. The fusion of data and computation distribution is the central principle guiding the development of a new architecture being developed by the authors, named SDAARC (Self Distributing Associative Architecture).

  • Exploring non-volatile main memory architectures for handheld devices

    As additional functionality is being added to contemporary handheld devices, the SoCs inside these devices are becoming increasingly complex. Similarly, the applications executing on these handhelds are beginning to exhibit an ever increasing memory footprint. To support these trends, main memory capacity of these SoCs has been increasing over time. Due to these developments, memory system's contribution to the overall system power has increased dramatically. Non-volatile memories have been used in server architectures to increase capacity as well as keep memory system's power consumption in check. However, in the handheld domain, where user experience and battery life are of paramount importance, the applicability of such technologies has not been widely studied. In this paper, we propose and evaluate a number of hybrid memory architectures using mobile DRAM and PCM. We show that intelligent memory architectures, cognizant of workload's memory access patterns can provide significant energy savings without compromising on user experience. Using proposed approach, we can devise architectures that exhibit significant energy savings with only a 2.8% performance loss.




Jobs related to Memory Architectures

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