IEEE Organizations related to Solid State Circuit Design

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Conferences related to Solid State Circuit Design

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Periodicals related to Solid State Circuit Design

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Most published Xplore authors for Solid State Circuit Design

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Xplore Articles related to Solid State Circuit Design

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Design of a solid-state neuron circuit for use in self-organizing systems

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1960

The artificial neuron or information-processing cell was designed primarily as a component for experimental neuron-network studies. With minor additions, it could be used for perceptron-type experiments. Each cell has ten exciting and ten inhibiting inputs, and each input has a separate weight associated with it. The operation of the cell depends upon the difference, between the weighted sums of the ...


Foreword integrated systems on a chip

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1980

None


Invited: The commercial and technical impact of integrated solid-state circuitry on tv and radio in europe

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1971

In Europe manufacturers have emphasized the development of linear ICs for consumer electronics. This report will discuss the resulting commercial and technical impact today and for the future.


N versus P channel for single-supply TTL compatibility

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1973

The application of N and P-channel processes to 5-V circuits with TTL inout/output compatibility will be discussed. Silicon-gate isoplanar processing with depletion-load devices will be covered.


Issues In High-speed Clocking

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1991

None


More Xplore Articles

Educational Resources on Solid State Circuit Design

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IEEE-USA E-Books

  • Design of a solid-state neuron circuit for use in self-organizing systems

    The artificial neuron or information-processing cell was designed primarily as a component for experimental neuron-network studies. With minor additions, it could be used for perceptron-type experiments. Each cell has ten exciting and ten inhibiting inputs, and each input has a separate weight associated with it. The operation of the cell depends upon the difference, between the weighted sums of the exciting and the inhibiting input signals.

  • Foreword integrated systems on a chip

    None

  • Invited: The commercial and technical impact of integrated solid-state circuitry on tv and radio in europe

    In Europe manufacturers have emphasized the development of linear ICs for consumer electronics. This report will discuss the resulting commercial and technical impact today and for the future.

  • N versus P channel for single-supply TTL compatibility

    The application of N and P-channel processes to 5-V circuits with TTL inout/output compatibility will be discussed. Silicon-gate isoplanar processing with depletion-load devices will be covered.

  • Issues In High-speed Clocking

    None

  • Editor's Overview, Dec. 1977

    This issue of the TRANSACTIONS presents a synopsis of the 1977 International Microwave Symposium. While the Symposium Digest gives in entirety the 152 papers, a few papers were selected for expansion and are contained herein. Also included is a resume of the Symposium functions, including the technical program, exhibits, social programs, and members of the Steering and Program Committees. Special attention is given to those we honored at the awards banquet.

  • ESSCIRC 2007

    None

  • Temperature-stable hyperchaotic oscillator

    A fourth-order circuit is described. It contains two negative impedance converters, two gyrators, two capacitors, and a comparator. The performance of the circuit is investigated both numerically and experimentally. The oscillator exhibits hyperchaotic behaviour and is characterized by two positive Lyapunov exponents. The circuit is found to be an extremely temperature-stable one.

  • A fault-tolerant 64K dynamic RAM

    A 64K MOS RAM, featuring 100ns worst-case column access time, 128 refresh cycles, and pin compatibility with 16K RAMs, will be described. Polysilicon bit lines provide a high cell/column capacitance ratio, while spare memory elements improve yield.

  • Wet electronic developments

    Two prototype solid-state switching devices and a multiplexer system were designed, fabricated, and successfully tested to demonstrate the use of solid- state devices under hydrostatic pressure cycling to 13,500 psi. The two switching devices were designed to use 24-Vdc voltages in controlling the application of 120-Vdc supply voltages, with a steady-state current of 10 A and surge currents of 100 A, to 1000-W incandescent lamps. One device, using silicon-controlled rectifiers, requires less than 0.06A and has a leakage current of about1\muA. The second device, using power transistors, requires less than 0.13 A and has a leakage current of about4\muA. The multiplexer provides 32 channels for control or instrumentation, but requires only four pressure-vessel penetrations. Testing of the prototype devices has demonstrated the feasibility of adapting solid-state devices for use in deep- ocean environments.



Standards related to Solid State Circuit Design

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Jobs related to Solid State Circuit Design

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