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Xplore Articles related to Sigma-delta Modulation

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Synthesis and design of a 4th order low-pass DT sigma-delta modulator in a 130nm cmos process

2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA), 2017

This paper summarizes the research work carried out during a doctorate studies, which is focused on the synthesis and design of a 4th Order ΣΔ Modulator in Discrete Time (DT) implemented in a 130nm CMOS process. By means of SIMSIDES the high-level simulation of the modulator is analyzed in order to translate the design specifications into a set of values ...


A wideband sigma-delta PLL based phase modulator with pre-distortion filter

2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT), 2012

A wideband sigma-delta PLL based phase modulator is presented in this paper. In the proposed architecture a pre-distortion filter is applied to balance the phase signals, compensating the suppression beyond the loop bandwidth. By properly balancing the PLL transmission characteristics, the data rate limitation is relieved to the sigma-delta PLL bandwidth. The applicable condition of pre-distortion filter is also analyzed ...


New high-order universal Sigma Delta modulator

Electronics Letters, 1995

A new high order sigma delta modulator called MSCL (multistage closed-loop) is presented. It uses a global feedback to lower the sensitivity to circuit imperfections and no digital prefiltering is required before summing up the output of each stage. Stable modulators can be realised to the sixth order. Simulation and experimental results are presented.<>


Modified comb decimator for high power-of-two decimation factors

2014 IEEE 5th Latin American Symposium on Circuits and Systems, 2014

This paper presents a modified two-stage comb decimation structure for Sigma- Delta Analog-to-Digital Converters (ADC) with high decimation factor, which can be implemented as a power of two. The proposed structure exhibits a decreased passband droop, as well as increased attenuations in the folding bands compared with the power and area efficient structures recently proposed in the literature. This is ...


An incremental sigma delta converter for compressive sensing applications

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

An analog-to-digital converter suitable for compressive sensing applications is presented. The converter is based on an incremental sigma-delta converter architecture and is able to directly acquire and convert to digital format compressive sensing measurements. A switched-capacitor circuit is proposed for the converter's hardware implementation. Simulations at the system and transistor levels validate the approach. The converter occupies a small area ...


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Educational Resources on Sigma-delta Modulation

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IEEE-USA E-Books

  • Synthesis and design of a 4th order low-pass DT sigma-delta modulator in a 130nm cmos process

    This paper summarizes the research work carried out during a doctorate studies, which is focused on the synthesis and design of a 4th Order ΣΔ Modulator in Discrete Time (DT) implemented in a 130nm CMOS process. By means of SIMSIDES the high-level simulation of the modulator is analyzed in order to translate the design specifications into a set of values such that the transistor level blocks be established by the desired performance of the proposed architecture. At the transistor level design, special attention is focused to the OTA, since this block is the main source of non-idealities in a Switched Capacitor (SC) Integrator. Moreover, the gm/IDmethodology is implemented into this stage as a tool to obtain the optimum circuit performance based on power consumption and better signal-to-noise ratio.

  • A wideband sigma-delta PLL based phase modulator with pre-distortion filter

    A wideband sigma-delta PLL based phase modulator is presented in this paper. In the proposed architecture a pre-distortion filter is applied to balance the phase signals, compensating the suppression beyond the loop bandwidth. By properly balancing the PLL transmission characteristics, the data rate limitation is relieved to the sigma-delta PLL bandwidth. The applicable condition of pre-distortion filter is also analyzed in this paper. The simulation results show that with PLL bandwidth of 1MHz the maximum phase error is no more than 10° and that RMS error is only 0.06° when transmitting 2.85 Mbps GMSK signals.

  • New high-order universal Sigma Delta modulator

    A new high order sigma delta modulator called MSCL (multistage closed-loop) is presented. It uses a global feedback to lower the sensitivity to circuit imperfections and no digital prefiltering is required before summing up the output of each stage. Stable modulators can be realised to the sixth order. Simulation and experimental results are presented.<>

  • Modified comb decimator for high power-of-two decimation factors

    This paper presents a modified two-stage comb decimation structure for Sigma- Delta Analog-to-Digital Converters (ADC) with high decimation factor, which can be implemented as a power of two. The proposed structure exhibits a decreased passband droop, as well as increased attenuations in the folding bands compared with the power and area efficient structures recently proposed in the literature. This is achieved by introducing a simple corrector filter at second CIC (Cascaded-Integrator-Comb) stage, such that it works at the rate, which is less than the high input rate by half of the decimation factor. The corrector filters depend only on the number of the cascaded equivalent combs. In that way the same corrector can be used for the comb decimator with different decimation factors but with the equal number of the cascaded combs. The comparison with the power and area efficient comb-based structures from literature, and the VHDL implementation, confirm the efficiency of the proposed structure.

  • An incremental sigma delta converter for compressive sensing applications

    An analog-to-digital converter suitable for compressive sensing applications is presented. The converter is based on an incremental sigma-delta converter architecture and is able to directly acquire and convert to digital format compressive sensing measurements. A switched-capacitor circuit is proposed for the converter's hardware implementation. Simulations at the system and transistor levels validate the approach. The converter occupies a small area of 0.047 mm2on a target 0.5 μm CMOS process. Thus, several of them can be implemented in parallel to achieve high conversion rates.

  • Power digital-to-analogue conversion using a sigma-delta modulator with controlled limit cycles

    A new technique for power digital-to-analogue conversion (DAC) is presented, based on a modified sigma-delta modulator (SDM) with a reduced transition rate in the bitstream. The technique is also shown to linearise the SDM.<>

  • Elimination of nonlinearity in sigma delta MEMS accelerometer

    This paper presents a method of eliminating nonlinearity in sigma delta MEMS accelerometer by keeping the proof mass fixed at the geometrically symmetrical position (the zero position). Published architectures on sigma delta MEMS accelerometer fail to maintain the proof mass at the zero position with nonzero static input. The output voltage is nonlinear to the input because of the displacement The proposed accelerometer system consists of sense element fabricated in SOG process and ASIC in 2P4M 0.35μm CHART CMOS process. Circuit implementations in ASIC generate excitation signal to sense the input acceleration and feedback signal to form electrostatic feedback force. Time division multiplexing is applied so that excitation and feedback signal can work simultaneously on the three plates sense element Both simulations with SIMULINK and test results show that the proof mass is maintained at the zero position with different static input within the range. A nonlinearity of 0.065%, 10μg noise floor and an input range of about ±3g are achieved.

  • Front-end of Bluetooth antenna with filter and sigma-delta modulator for wireless power transfer

    The proposed a front-end of Bluetooth antenna with filter circuits and a continuous-time quadrature band pass sigma-delta (ΣΔ) modulator integration with CICFF topology are presented for wireless charging application. Continuous-time quadrature band pass sigma-delta (ΣΔ) modulator with Bluetooth link communication in A4WP and control strategy has been adopted in state-of- the-art wireless power transfer (WPT) applications to meet power demand with the highest efficiency against coupling and load variations. The proposed circuits used WuRx technology for power saving and produce one path combo design for Bluetooth antenna and wireless charging coil.

  • A low-power dual-mode sigma-delta modulator using charge-steering opamps

    The charge-steering concept is applied to opamps as a means of conserving power. The opamp is the heart of the sigma-delta modulator circuit and the part in which the major portion of the power consumption is dissipated. This work presents a dual mode sigma-delta modulator for two wireless standards, GSM and Bluetooth. It achieves dual-mode operation with the same sampling frequency, while the capacitor values and the embedded quantizer are changed. The modulator achieves 65/50 dB SNR over a bandwidth of 0.2/1 MHz with an over sampling ratio of 120/24 and consumes 3.7/3.6 mW of power in GSM/Bluetooth modes, respectively. The charge-steering opamp consumes about 40% of the total power consumption.

  • VHDL-AMS model of delta-sigma (ΔΣ) modulator for A/D converter in mems interface circuit

    In the paper, VHDL-AMS model of delta-sigma (ΔΣ) for MEMS A/D conversion circuits has been developed. The developed model allows to simulate the change of the impulses sequence at the output of the delta-sigma modulator depending on the input signal and also to conduct the analysis of the delta-sigma modulator at the block design level.



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