IEEE Organizations related to Side-channel Attacks

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Conferences related to Side-channel Attacks

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Periodicals related to Side-channel Attacks

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Most published Xplore authors for Side-channel Attacks

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Xplore Articles related to Side-channel Attacks

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Security-aware Task Mapping Reducing Thermal Side Channel Leakage in CMPs

IEEE Transactions on Industrial Informatics, None

Chip Multi-Processor (CMP) suffers from growing threats on hardware security in recent years, such as side channel attack, hardware trojan infection and chip clone, etc. In the paper, we propose a security-aware task mapping method to reduce the information leakage from CMP thermal side channel. First, we construct a mathematical function which can estimate the CMP security cost corresponding to ...


Type and Leak Your Ethnicity on Smartphones

ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2019

This paper provides some preliminary results for a possible novel side channel attack on Android smart phones. This attack collects accelerometer readings when users type on soft keyboards. The work has the following two parts: 1) differentiate users based on sensor readings and 2) identify whether the user belongs to a particular nationality i.e., Chinese in this work. This work ...


Secure high-performance computer architectures: Challenges and opportunities

2018 IEEE 25th International Conference on High Performance Computing (HiPC), 2018

Summary form only given. Recent work has shown that architectural isolation can be violated through software side channel attacks that exploit microarchitectural performance optimizations such as speculation to leak secrets. While turning off microarchitectural optimizations can preclude some classes of attacks, we argue that performance and security do not have be in conflict, provided processors are designed with security in ...


Leveraging 3D Packaging Technology to Enhance Integrated Circuits Security and Reliability

2018 19th International Conference on Electronic Packaging Technology (ICEPT), 2018

Hardware security plays an important role in the information security field and has gained significant interests from both industry and academic communities. 3D integration technology, which enables ICs to be stacked in the vertical dimension and provides smaller form factor and higher performance, has been extensively researched in the past. From the security and reliability perspectives, 3D integration technology also ...


On the Detection of Side-Channel Attacks

2018 IEEE 23rd Pacific Rim International Symposium on Dependable Computing (PRDC), 2018

Threats posed by side-channel and covert-channel attacks exploiting the CPU cache to compromise the confidentiality of a system raise serious security concerns. This applies especially to systems offering shared hardware or resources to their customers. As eradicating this threat is practically impeded due to performance implications or financial cost of the current mitigation approaches, a detection mechanism might enhance the ...


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Educational Resources on Side-channel Attacks

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IEEE.tv Videos

IMS 2014: STEM at IMS
Doing the Right Thing: Social Implications of Technology (Member Access)
IMS 2011 Microapps - Digital Radio Testing Using an RF Channel Replicator
Lionel Briand on Software Engineering
Brooklyn 5G Summit 2014: Channel Modeling and System Capacity with Dr. Tim Thomas and Dr. A Ghosh
Brooklyn 5G - 2015 - Andreas F. Molisch - Channel Measurements for Massive MIMO
Brooklyn 5G Summit: Channel Models: Key to 5G Air-Interface Technology
Regular Expression Matching with Memristor TCAMs - Cat Graves - ICRC 2018
Brooklyn 5G Summit 2014: Tommi Jamsa on METIS Channel Modeling Activities
IMS 2014: Wideband mmWave Channels: Implications for Design and Implementation of Adaptive Beam Antennas
Brooklyn 5G Summit 2014: Jonas Medbo on 5G Channel Modeling Challenges
Brooklyn 5G - 2015 - Dr. Amitabha Ghosh & Dr. Timothy A. Thomas - 5G Channel Modeling from 6 to 100 GHz: Critical Modeling Aspects and Their Effect on System Design and Performance
George Oikonomou’s Paper: Traffic Forensics for IPv6-Based Wireless Sensor Networks and the IoT: WF-IoT 2016
Brooklyn 5G Summit 2014: Channel Measurements Summary by Ted Rappaport
28 GHz mmWave Channel Sounder: From Inception to Reality - Arun Ghosh: Brooklyn 5G Summit 2017
Brooklyn 5G - 2015 - George MacCartney - MmWave Channel Models - A Unified Approach for 5G Standardization and Modern Design
Keynote Isaac Ben-Israel - ETAP Forum Tel Aviv 2016
Shao-Chuan Lee: SandUSB: An Installation-Free Sandbox for USB Peripherals: WF-IoT 2016
IMS MicroApps: Nonlinear Co-Simulation with Real-Time Channel Measurements
Brooklyn 5G 2016: Panel Moderator Dr. Ted Rappaport on Channel Models and Spectrum

IEEE-USA E-Books

  • Security-aware Task Mapping Reducing Thermal Side Channel Leakage in CMPs

    Chip Multi-Processor (CMP) suffers from growing threats on hardware security in recent years, such as side channel attack, hardware trojan infection and chip clone, etc. In the paper, we propose a security-aware task mapping method to reduce the information leakage from CMP thermal side channel. First, we construct a mathematical function which can estimate the CMP security cost corresponding to a given mapping result. Then, we develop a greedy mapping algorithm which automatically allocates all threads of an application to a set of proper cores, such that the total security cost is optimized. Finally, we perform extensive experiments to evaluate our method. The experimental results show that our security-aware mapping effectively decreases the CMP side channel leakage. Compared to two existing task mapping methods, LS (a standard Linux scheduler) and NS (a thermal-aware mapping technique), our method reduces Side-channel Vulnerability Factor (SVF) by up to 19% and 7%, respectively. Moreover, our method also gains higher computational efficiency, with improvement in MIPS achieving up to 100% against NS and up to 33% against LS.

  • Type and Leak Your Ethnicity on Smartphones

    This paper provides some preliminary results for a possible novel side channel attack on Android smart phones. This attack collects accelerometer readings when users type on soft keyboards. The work has the following two parts: 1) differentiate users based on sensor readings and 2) identify whether the user belongs to a particular nationality i.e., Chinese in this work. This work uses a novel signal processing technique along with random forest machine learning algorithm to extract unique features belong to Chinese nationalities. We collected more than 2000 keystrokes data from six users where three of them are Chinese nationals. Our model has correctly identified 86% of the sensor data to classify Chinese nationality. Since any apps installed on Android device can listen to the accelerometer sensor data, the side channel attack presented in this work demonstrates another potential privacy vulnerability which could be exploited by malicious apps for targeted activities such as advertisements.

  • Secure high-performance computer architectures: Challenges and opportunities

    Summary form only given. Recent work has shown that architectural isolation can be violated through software side channel attacks that exploit microarchitectural performance optimizations such as speculation to leak secrets. While turning off microarchitectural optimizations can preclude some classes of attacks, we argue that performance and security do not have be in conflict, provided processors are designed with security in mind. We espouse a principled approach to eliminating entire attack surfaces through microarchitectural isolation, rather than plugging attack-specific privacy leaks. We argue that minimal modifications to hardware can defend against all currently-practical side channel attacks and without significant performance impact. As an application of this approach, we describe the Sanctum processor architecture that offers strong provable isolation of software modules running concurrently and sharing resources, and Sanctoom, a speculative, out-of-order variant with similar properties. These processors provide isolation even when large parts of the operating system are compromised, and their open-source implementations allow security properties to be independently verified.

  • Leveraging 3D Packaging Technology to Enhance Integrated Circuits Security and Reliability

    Hardware security plays an important role in the information security field and has gained significant interests from both industry and academic communities. 3D integration technology, which enables ICs to be stacked in the vertical dimension and provides smaller form factor and higher performance, has been extensively researched in the past. From the security and reliability perspectives, 3D integration technology also provides a unique perspective to cope with the security threats occurred in different phases of an IC's life cycle. In this paper, the advantages and challenges of 3D integration technology have been analyzed from security and reliability perspectives. Furthermore, a novel low cost wet etching based interposer structure was introduced to realize high security packaging of ICs, which owns package level metal shielding network to prevent side channel information leakage and to detect reverse-engineering attack in real time. The thermal and electromagnetic properties of the designed package structure were examined by finite element method and the fabrication process was also systematically discussed.

  • On the Detection of Side-Channel Attacks

    Threats posed by side-channel and covert-channel attacks exploiting the CPU cache to compromise the confidentiality of a system raise serious security concerns. This applies especially to systems offering shared hardware or resources to their customers. As eradicating this threat is practically impeded due to performance implications or financial cost of the current mitigation approaches, a detection mechanism might enhance the security of such systems. In the course of this work, we propose an approach towards side- channel attacks detection, considering the specificity of cache-based SCAs and their implementations.

  • Attacking AES implementations using correlation power analysis on ZYBO Zynq-7000 SoC board

    Differential power analysis (DPA) and its enhanced variant, correlation power analysis (CPA), are one of the most common side channel attacks today. A dedicated hardware platform is often used when performing this kind of attack for experimental purposes. In this paper, we present the modifications of a common ZYBO board, that are necessary to perform the CPA attack. We illustrate the whole process of attacking both software and hardware implementations of AES-128 and we present our experimental results.

  • Combining algebraic and side channel attacks on stream ciphers

    A cryptanalysis technique can be termed successful if its complexity is better than brute force attack, even though it may not be practically feasible due to high complexity. However, it is a proven fact that combining different type of attack techniques in past has paid dividends with regards to overall complexity. We, in this paper propose novel idea of combining algebraic and side channel attacks on stream ciphers. Algebraic cryptanalysis has a high cost when pitched against stream ciphers with nonlinear update and for side channel attacks, adversary needs to have a continued access to cipher's implementation. On the other hand combining both these attacks can overcome their individual shortcomings to a great extent, thereby making it practically feasible. Algebraic and side channel attacks have been earlier combined on block ciphers, but no work on applying such attacks against stream ciphers has been published so far.

  • Single Trace Side Channel Analysis on Quantum Key Distribution

    The security of current key exchange protocols such as Diffie-Hellman key exchange is based on the hardness of number theoretic problems. However, these key exchange protocols are threatened by weak random number generators, advances to CPU power, a new attack from the eavesdropper, and the emergence of a quantum computer. Quantum Key Distribution (QKD) addresses these challenges by using quantum properties to exchange a secret key without the risk of being intercepted. Recent developments on the QKD system resulted in a stable key generation with fewer errors so that the QKD system is rapidly becoming a solid commercial proposition. However, although the security of the QKD system is guaranteed by quantum physics, its careless implementation could make the system vulnerable. In this paper, we proposed the first side-channel attack on plug-and-play QKD system. Through a single electromagnetic trace obtained from the phase modulator on Alice's side, we were able to classify the electromagnetic trace into four classes, which corresponds to the number of bit and basis combination in the BB84 protocol. We concluded that the plug- and-play QKD system is vulnerable to side-channel attack so that the countermeasure must be considered.

  • Correlation power analysis attack against STT-MRAM based cyptosystems

    Summary form only given. Emerging technologies such as Spin-transfer torque magnetic random-access memory (STT-MRAM) are considered potential candidates for implementing low-power, high density storage systems. The vulnerability of such nonvolatile memory (NVM) based cryptosystems to standard side-channel attacks must be thoroughly assessed before deploying them in practice. In this paper, we outline a generic Correlation Power Analysis (CPA) attack strategy against STT-MRAM based cryptographic designs using a new power model. In our proposed attack methodology, an adversary exploits the power consumption patterns during the write operation of an STT-MRAM based cryptographic implementation to successfully retrieve the secret key. In order to validate our proposed attack technique, we mounted a CPA attack on MICKEY-128 2.0 stream cipher design consisting of STT-MRAM cells with Magnetic Tunnel Junctions (MTJs) as storage elements. The results of the experiments show that the STT-MRAM based implementation of the cipher circuit is susceptible to standard differential power analysis attack strategy provided a suitable hypothetical power model (such as the one proposed in this paper) is selected. In addition, we also investigated the effectiveness of state-of-the-art side- channel attack countermeasures for MRAMs and found that our proposed scheme is able to break such protected implementations as well.

  • Secure certificateless signature resisting to continual leakage attacks

    Recently, numerous leakage-resilient cryptographic schemes have been proposed to resist side-channel attacks which adopt several properties resulting from practical implementations of cryptographic protocols/schemes to leak partial information of secret (or private) keys. Certificateless public key cryptography solves both certificate management problem in conventional public key cryptography and the key escrow problem in ID-based public key cryptography. However, there is little work on studying the design of certificateless cryptographic schemes resisting to side-channel attacks. In the article, the first leakage-resilient certificateless signature (LR-CLS) scheme is proposed. In the generic bilinear group model, the proposed scheme is demonstrated to possess existential unforgeability against adaptive chosen- message attacks under the continual leakage model for both Type I and Type II adversaries.



Standards related to Side-channel Attacks

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Jobs related to Side-channel Attacks

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