IEEE Organizations related to Single Event Upsets

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Conferences related to Single Event Upsets

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Periodicals related to Single Event Upsets

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Most published Xplore authors for Single Event Upsets

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Xplore Articles related to Single Event Upsets

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SEE Measurements and Simulations Using Mono-Energetic GeV-Energy Hadron Beams

IEEE Transactions on Nuclear Science, 2013

Single Event Upset (SEU) measurements were performed on the ESA SEU Monitor using mono-energetic GeV-energy hadron beams available in the North Experimental Area at CERN. A 400 GeV proton beam in the H4IRRAD test area and a 120 GeV mixed pion and proton beam at the CERN-EU high Energy Reference Field facility (CERF) were used for this purpose. The resulting ...


Single event transients of scan flip-flop and an SET-immune redundant delay filter (RDF)

2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2013

Heavy-ion tests on 65nm CMOS Flip-Flops with different topologies are conducted to investigate their susceptibility to single event upsets (SEUs) and single event transients (SETs). The test results show that SETs on scan- enable node (SE) may cause a large number of SEUs, and the conventional delay filter is vulnerable to SETs, which can reduce the efficiency of delay-filter Flip-Flops. ...


Study of a delayed single-event effect in the Muller C-element

2016 21th IEEE European Test Symposium (ETS), 2016

We study the behavior of the Muller C-element, a fundamental building block in asynchronous design, under SETs. Beyond the expected reactions to the injected SETs - namely immediate state flip or pulse at the output - we also observed an new kind of behavior for the Muller C-element, namely a delayed state flip. In this paper we give a closer ...


Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch

IEEE Transactions on Nuclear Science, 2013

This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi- bit-latch (MBL) without performance degradation by applying well-slits. The area overhead in an MBL macro for processor design, which includes a clock buffer and a checker, is only 5.4% in a 28 nm technology. Sixty-hour accelerated neutron irradiation test observed no MBUs in the MBL with well- slits. The ...


Simulation of Proton Induced SET in Linear Devices and Assessment of Sensitive Thicknesses

2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2015

This study aims to accurately determine analog SET proton cross sections derived from heavy ion data using gateway tools such as METIS, SIMPA or the more recent METIS approach we developed within Airbus Group. We validate the methodology on three linear devices and show promising results. Especially, METIS could be used in a reversed manner to determine the sensitive thickness ...


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Educational Resources on Single Event Upsets

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IEEE.tv Videos

An IEEE IPC Special Session with X. Chen from Nokia Bell Labs
Energy Efficient Single Flux Quantum Based Neuromorphic Computing - IEEE Rebooting Computing 2017
Single Frame Super Resolution: Fuzzy Rule-Based and Gaussian Mixture Regression Approaches
A Comparison Between Single Purpose and Flexible Neuromorphic Processor Designs: IEEE Rebooting Computing 2017
Neuromorphic computing with integrated photonics and superconductors - Jeffrey Shainline: 2016 International Conference on Rebooting Computing
Broadband IQ, Image Reject, and Single Sideband Mixers: MicroApps 2015 - Marki Microwave
IMS MicroApps: Single Chip LNA on 0.25um SOS for SKA Midband Receiver
Maker Faire 2008: Spectrum's Digital Clock Contest Winner
Single Die Broadband CMOS Power Amplifier and Tracker with 37% Overall Efficiency for TDD/FDD LTE Applications: RFIC Industry Forum
Nanophotonic Devices for Quantum Information Processing: Optical Computing - Carsten Schuck at INC 2019
Multiobjective Quantum-inspired Evolutionary Algorithm and Preference-based Solution Selection Algorithm
A Wideband Single-PLL RF Receiver for Simultaneous Multi-Band and Multi-Channel Digital Car Radio Reception: RFIC Industry Showcase
Approximate Dynamic Programming Methods A Unified Framework
Handling of a Single Object by Multiple Mobile Robots based on Caster-Like Dynamics
Single Crystal AlGaN Bulk Acoustic Wave Resonators on Silicon Substrates with High Electromechanical Coupling: RFIC Industry Showcase
IEEE IPC Special Session with Domanic Lavery of UCL
SIMD Programming in VOLK, the Vector-Optimized Library of Kernels
Ciena Corp - IEEE Spectrum Emerging Technology Award, 2019 IEEE Honors Ceremony
Stochastic Single Flux Quantum Neuromorphic Computing using Magnetically Tunable Josephson Junctions - Stephen Russek: 2016 International Conference on Rebooting Computing
Multi-Standard 5Gbps to 28.2Gbps Adaptive, Single Voltage SerDes Transceiver with Analog FIR and 2-Tap Unrolled DFE in 28nm CMOS: RFIC Interactive Forum 2017

IEEE-USA E-Books

  • SEE Measurements and Simulations Using Mono-Energetic GeV-Energy Hadron Beams

    Single Event Upset (SEU) measurements were performed on the ESA SEU Monitor using mono-energetic GeV-energy hadron beams available in the North Experimental Area at CERN. A 400 GeV proton beam in the H4IRRAD test area and a 120 GeV mixed pion and proton beam at the CERN-EU high Energy Reference Field facility (CERF) were used for this purpose. The resulting cross section values are presented and discussed as well as compared to the several hundred MeV case (typical for standard test facilities) from a physical interaction perspective with the intention of providing a more general understanding of the behavior. Moreover, the implications of the cross section dependence with energy above the several hundred MeV range are analyzed for different environments. In addition, analogous measurements are proposed for Single Event Latchup (SEL), motivated by discussed simulation results. Finally, a brief introduction of the future CHARM (CERN High-energy AcceleratoR Mixed facility) test installation is included.

  • Single event transients of scan flip-flop and an SET-immune redundant delay filter (RDF)

    Heavy-ion tests on 65nm CMOS Flip-Flops with different topologies are conducted to investigate their susceptibility to single event upsets (SEUs) and single event transients (SETs). The test results show that SETs on scan- enable node (SE) may cause a large number of SEUs, and the conventional delay filter is vulnerable to SETs, which can reduce the efficiency of delay-filter Flip-Flops. A new delay filter named redundant delay filter (RDF) is proposed to improve the SET immunity.

  • Study of a delayed single-event effect in the Muller C-element

    We study the behavior of the Muller C-element, a fundamental building block in asynchronous design, under SETs. Beyond the expected reactions to the injected SETs - namely immediate state flip or pulse at the output - we also observed an new kind of behavior for the Muller C-element, namely a delayed state flip. In this paper we give a closer analysis of this effect and identify its enabling conditions.

  • Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch

    This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi- bit-latch (MBL) without performance degradation by applying well-slits. The area overhead in an MBL macro for processor design, which includes a clock buffer and a checker, is only 5.4% in a 28 nm technology. Sixty-hour accelerated neutron irradiation test observed no MBUs in the MBL with well- slits. The proposed mitigation technique achieved excellent robustness against MBU without any increase in SBU rate. The MBL with the proposed mitigation technique helps improve reliability of electronic devices.

  • Simulation of Proton Induced SET in Linear Devices and Assessment of Sensitive Thicknesses

    This study aims to accurately determine analog SET proton cross sections derived from heavy ion data using gateway tools such as METIS, SIMPA or the more recent METIS approach we developed within Airbus Group. We validate the methodology on three linear devices and show promising results. Especially, METIS could be used in a reversed manner to determine the sensitive thickness based on the knowledge of both proton and heavy ion cross sections.

  • Handling Soft Error in Embedded Software for Networking System

    Single event upset (SEU) is a well known and documented phenomenon that affects electronic circuitry. These events are caused by either atmospheric neutrons or alpha particles emitted by trace impurities in the silicon processing and packaging materials. The error in device output or operation caused by SEU is called soft error. Soft error is not software defects, but instead refers to a hardware data corruption that does not involve permanent chip damage. Soft errors can lead to catastrophic failures for embedded system. Due to the nature of the soft error, it is almost impossible to prevent them. Based on the impact severity, the recommended handling is to detect and correct them, called mitigation methodologies. The mitigation strategies are implemented in embedded software for networking system. This paper presents a comprehensive framework for single-event upset (SEU) mitigation methodologies for networking system. To achieve this goal we start by defining the SEU mitigation strategy as a combination of chip level methods and system level handling methods. Given a particular SEU chip level or system level mitigation choice, we propose first categorizing the SEU Failure In Time (FIT) into different time window bins based on SEU recovery time. Then we analyze the impact of each mitigation strategy, results in the FIT value change in each bin. This framework enables the engineers to do the SEU mitigation design in early product development phase. A user-friendly Excel tool is also developed to make the complicated model easy to use. The embedded system like networking device can be modeled using the tool at an early stage to support design decisions and trade-offs related to potentially costly implementation.

  • Detecting Single Event Upsets in Embedded Software

    The past decade has seen explosive growth in the use of small satellites. Within this domain, there has been a growing trend to place more responsibility on the flight software (versus hardware) and an increasing adoption of consumer-grade microprocessors to satisfy this desire for increased processing capability while still minimizing size, weight, and power parameters. These consumer-grade processors, however, are more susceptible to cosmic radiation and the occurrence of single event upsets. In this paper, we examine software-centric checks to detect the occurrence of such upset events in modern microprocessors.

  • Single-Event Upsets Characterization & Evaluation of Xilinx UltraScale™ Soft Error Mitigation (SEM IP) Tool

    This paper examines the single-event upset response of the Xilinx UltraScale Soft Error Mitigation (SEM IP) software tool irradiated with a 64MeV proton source. The SEM SEU results are then compared to accelerated particle testing results for the Xilinx 20nm Kintex family, collected at LANSCE and Crocker, to evaluate its capability to detect & collect SEU accurately. Furthermore, Xilinx 20nm stacked silicon on interposer (SSI) technology SEU response is characterized. SEU and MBU results are presented.

  • Development of a radiation-hardened standard cell library for 65nm CMOS technology

    We have developed a radiation-hardened standard cell library for space applications based on the commercial 65nm CMOS technology process. The standard cells are designed using some radiation-hardened (RH) techniques, and the effects of these RH approaches have been validated. Also this 65nm CMOS RH standard cell library has been characterized to support the verilog to GDSII design flow, and the designed radiation tolerant features of this library are: TID > 500 Krad(Si), SEL > 100 MeV·cm2/mg, SEU > 37 MeV cm2/mg.

  • Simulation of single-event upset in power MOSFETs

    The effects of striking of ions on a low-voltage power MOSFET have been investigated in this work. Special emphasis has been given on the study of Single Event Gate Rupture (SEGR) event. The physics-based device simulation tools: Silvaco ATHENA and ATLAS are used for process and device simulations and characterize the electrical properties of a power MOSFET suitable for space applications.



Standards related to Single Event Upsets

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Jobs related to Single Event Upsets

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