Semiconductor Device Packaging
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[1992 Proceedings] Electrical Performance of Electronic Packaging, 1992
International Report on Wafer Level Reliability Workshop, 1992
COMPCON '77, 1977
ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference, 1996
A single `chip' IF-to-Digital converter sub-system containing Low Noise Amplifiers, AGC, down-conversion mixers, oscillators, baseband amplifiers, references and an A/D converte is presented. Mixed analog-digital circuit design and packaging techniques achieve a high level of integration using standard semiconductor processes. Measured results show that the IC can operate on IF signals between 30MHz-85MHz and decode transmissions up to 64QAM either ...
Proceedings International Symposium on Advanced Packaging Materials. Processes, Properties and Interfaces (IEEE Cat. No.99TH8405), 1999
In semiconductor manufacturing, front end scaling (i.e. Moore's Law) continues to hold for the forseeable future. Unfortunately, the back-end processes of package assembly, burn-in and test all require wafer singulation before any of these processes can occur. Singulation immediately forces a linearly increasing cost model, scaling with the number of die/wafer, and prevents a wafer scaling cost model. FormFactor looked ...
Amalga: Alternative to MEMS Technology for Miniature RF Components
KeyTalks: 3D Packaging of Power Products
Why Join the IEEE Electronics Packaging Society
Semiconductor Laser Development at Hisense Photonics - Yanfeng Lao - IPC 2018
Heterogeneous Photonic Packaging - John Osenbach - IPC 2018
Honors 2020: Chenming Hu Wins the IEEE Medal of Honor
APEC 2018 - full live-stream replay
2015 IEEE Honors: IEEE Jun-ichi Nishizawa Medal - Dimitri A. Antoniadis
Overview of SDRJ - Yoshihiro Hayashi at INC 2019
The Era of AI Hardware - 2018 IEEE Industry Summit on the Future of Computing
Micrel Ripple Blocker
Pt. 2: Electronic & Photonic (Co)Packaging Technologies - Bill Bottoms - Industry Panel 2, IEEE Globecom, 2019
3D Power Packaging Made Real with Embedded Component and Substrate Technologies - P.M. Raj, APEC 2018
IMS 2011 Microapps - Beyond the S-Parameter: The Benefits of Nonlinear Device Models
The Future of Semiconductor: Moore's Law Plus - IEEE Rebooting Computing Industry Summit 2017
APEC 2012 - Dan Kinzer Plenary
ASC-2014 SQUIDs 50th Anniversary: 2 of 6 - John Clarke - The Ubiquitous SQUID
2011 Medal of Honor - Morris Chang
A single `chip' IF-to-Digital converter sub-system containing Low Noise Amplifiers, AGC, down-conversion mixers, oscillators, baseband amplifiers, references and an A/D converte is presented. Mixed analog-digital circuit design and packaging techniques achieve a high level of integration using standard semiconductor processes. Measured results show that the IC can operate on IF signals between 30MHz-85MHz and decode transmissions up to 64QAM either in NTSC or PAL systems. Key performance factors include 63dB stable gain, 50dB IMD3, 40dB AGC range, 9dB input Noise Figure and 40Msps A/D conversion rate.
In semiconductor manufacturing, front end scaling (i.e. Moore's Law) continues to hold for the forseeable future. Unfortunately, the back-end processes of package assembly, burn-in and test all require wafer singulation before any of these processes can occur. Singulation immediately forces a linearly increasing cost model, scaling with the number of die/wafer, and prevents a wafer scaling cost model. FormFactor looked at the issues preventing wafer- level back-end processing, and postulated that the highest probability of success would require an approach that integrated the previously separate disciplines of materials, package assembly, burn-in, and test. The connection element to the test and burn-in systems was identified as a primary enabler or inhibitor. In this paper, we briefly describe a wafer-level back-end flow, the chip scale package that this process defines, and the early results observed with this flow and package.
A ceramic BGA packaging technology for broadband applications such as LMDS and SONET/SDH is described. The package is designed for the bandwidth of DC-32 GHz. Manufactured on VIA/PLANE/sup (R)/ using semiconductor processing techniques in an array format, it provides the ability to assemble and test the devices in arrays for maximum productivity. The paper describes the electromagnetic modeling, design, manufacture and testing of the package. Its electrical performance is compared with the theoretical model. The thermal model of the package with device on PCB is also presented. The package attributes are compared with the conventional leaded, microstrip/stripline and leadless formats.
Developing testable products cost-effectively requires that a standard, such as JTAG and the IEEE P-1149, be adopted. The system developer and semiconductor manufacturer need to share in this development effort to accelerate adoption. The system developer must gain a better understanding of the total cost of ownership for a testable vs. a nontestable product and the semiconductor manufacturer must be willing to provide initial product offerings before a well defined and quantified market exists. Efforts must be put in place to implement standards in software tools and data formats required to support test.<>
The qualification of the die attach of semiconductor devices is a very important element of predicting the reliability of the package, as the temperature of the chip is strongly affected by the quality of the die attach. This paper describes our latest findings on die attach quality testing of semiconductor devices using short term thermal transient measurements. Using estimates from simulations as well as from measured structure functions of power transistors with known die attach quality we found that cca the first 100ms section of thermal transients is sufficient to draw conclusion on die attach quality. In case of in-line application of the short term thermal transient measurements however, there are different difficulties such as lack of time for K-factor calibration of the individual devices under test. In this paper we describe certain techniques which have been validated on large number of power LEDs with the aim of application in in line testing of die attach quality.
Temperature cycling tests are commonly used in the semiconductor industry to determine the number of cycles to failure and to predict reliability of the solder joints in the surface mount technology packages. In this paper, the thermomechanical fatigue of Pb40/Sn60 solder joint in a leadless ceramic chip carrier package is studied and temperature cycling test is simulated by using a finite element procedure with the disturbed state concept (DSC) constitutive models. The progress of disturbance (damage) and the energy dissipated in the solder joint during thermal cycling are predicted. It is shown that the disturbance criterion used follows a similar path as the energy dissipation in the system. Moreover, the comparisons between the test data and the finite element analysis show that a finite element procedure using the DSC material models can be instrumental in reliability analysis and to predict the number of cycles to failure of a solder joint. Furthermore, the analysis gives a good picture of the progress of the failure mechanism and the disturbance in the solder joint.
The rapid incursion of new technologies such as MEMS and smart sensor device manufacturing requires new tailor-made packaging designs. In many applications these devices are exposed to humid environments. Since the penetration of moisture into the package may result in internal corrosion or shift of the operating parameters, the reliability testing of hermetically sealed packages has become a crucial question in the semiconductor industry. Thermal transient testing, a well known technique for thermal characterization of IC packages can be a suitable method for detecting hermeticity failures in packaged semiconductor and MEMS devices. In the paper this measuring technique is evaluated. Experiments were done on different measurement setups at different environment temperature and RH levels. Based on the results, a new method for package hermeticity testing is proposed.
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Semiconductor Packaging Engineer
SUNY Polytechnic Institute