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IEEE Approved Draft Standard for VHDL Language Reference Manual

IEEE P1076/D13, July 2019, 2019

VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary ...


IEEE Draft Standard for VHDL Language Reference Manual

IEEE P1076/D11, July 2019, 2019

VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary ...


Hardware Implementation of Sigmoid Activation Functions using FPGA

2019 IEEE 15th International Conference on the Experience of Designing and Application of CAD Systems (CADSM), 2019

The methods of approximation of the sigmoid function are developed and modified, using piecewise linear approximation and approximation by a second order polynomial. The estimation of the accuracy of approximation by these methods of sigmoid function and its derivative is performed. The considered methods are implemented on FPGA using VHDL. The comparison of the required hardware resources and performance is ...


Stage-oriented, Mixed Design Methodology for Image Processing Using VHDL and Python

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", 2019

The data analysis could be a very time consuming process during the hardware design on FPGA platforms. The verification process of designed modules is important at each step of a design process. In some cases standard methods for data analysis are insufficient, especially when the data representation are taken into assessment methods. In image processing systems based on FPGA there ...


Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture

2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019

The research work presented in this paper is about a holistic tool-chain for generating, configuring and evaluating application-specific Coarse-Grained Reconfigurable Array (CRGA) architectures. This development was part of a large EU funded project with the name EXTRA. The reduced complexity of the architecture in comparison to fine-grained architectures like FPGAs is exploited to evaluate the Just-in-Time generation of VCGRA configurations. ...



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  • IEEE Approved Draft Standard for VHDL Language Reference Manual

    VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.

  • IEEE Draft Standard for VHDL Language Reference Manual

    VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.

  • Hardware Implementation of Sigmoid Activation Functions using FPGA

    The methods of approximation of the sigmoid function are developed and modified, using piecewise linear approximation and approximation by a second order polynomial. The estimation of the accuracy of approximation by these methods of sigmoid function and its derivative is performed. The considered methods are implemented on FPGA using VHDL. The comparison of the required hardware resources and performance is given.

  • Stage-oriented, Mixed Design Methodology for Image Processing Using VHDL and Python

    The data analysis could be a very time consuming process during the hardware design on FPGA platforms. The verification process of designed modules is important at each step of a design process. In some cases standard methods for data analysis are insufficient, especially when the data representation are taken into assessment methods. In image processing systems based on FPGA there are various methods to support engineers in development of desired architecture. Some of them are based on scoping hardware signals in running device. It is also possible to scope signals in a simulation environment. In addition there are also high-level abstraction layer of data analysis methods based on Matlab, Python and similar tools. The unique image processing architecture developed by authors could not be upgraded with support of existing co-design methods. This is why stage-oriented, mixed design methodology was performed to support FPGA hardware development for faster prototyping and debugging with Vivado simulator tool and Python language. Presented approach was used to improve image processing design operating with ultra high resolution images (from 5 Mpix up to 70 Mpix).

  • Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture

    The research work presented in this paper is about a holistic tool-chain for generating, configuring and evaluating application-specific Coarse-Grained Reconfigurable Array (CRGA) architectures. This development was part of a large EU funded project with the name EXTRA. The reduced complexity of the architecture in comparison to fine-grained architectures like FPGAs is exploited to evaluate the Just-in-Time generation of VCGRA configurations. The manuscript presents the tool-chain that is responsible for the implementation of applications on the coarse-grained architecture. In particular, the tools for partitioning the applications, mapping the partitions and controlling the execution of the entire application on the target architecture will be examined. In addition, both the user interface and the interfaces between the components of the tool-chain are described. Subsequently, the presented tools are evaluated using a practical example and various metrics. We show, that the creation of configurations for the presented architectures can be carried out rapidly and therefore the generation of new configurations at run-time is feasible.

  • Experiencing Technology Independence

    In this paper we present an embedded systems design flow, supporting variations in technology — hardware vs. software — at implementation time. The work builds on seasoned and new approaches, tools and techniques, such as software production lines, FPGA design, and high level synthesis. We define the necessary context for such a design flow to succeed, and introduce supporting tools and interfaces to enable the designer to take decisions, which are further automatically transferred into the synthesis phases. We exemplify our solutions on a motor controller design, considering several features that are potentially required to be implemented, and where all the elements are possible to be implemented either as hardware or software modules.

  • HDL FSM Code Generation Using a MIPS-based Assembler

    The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs. This paper proposes the use of a MIPS- based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.

  • IEEE Draft Standard VHDL Analog and Mixed-Signal Extensions

    The IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems, is defined in this standard. The language, also informally known as VHDL-AMS, is built on IEEE Std 1076-2008 (VHDL) and extends it with additions and changes to provide capabilities of writing and simulating analog and mixed-signal models. (Additional downloadable files are available for this standard at http://standards.ieee.org/downloads/1076/1076.1-2017/)

  • IEEE Draft Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language

    The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (The PDF of this standard is available at no cost at http://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80 compliments of Accellera Systems Initiative)

  • A High-level Implementation Framework for Non-Recurrent Artificial Neural Networks on FPGA

    This paper presents a fully parametrized framework, entirely described in VHDL, to simplify the FPGA implementation of non-recurrent Artificial Neural Networks (ANNs), which works independently of the complexity of the networks in terms of number of neurons, layers and, to some extent, overall topology. More specifically, the network may consist of fully-connected, max-pooling or convolutional layers which can be arbitrarily combined. The ANN is used only for inference, while back-propagation is performed off-line during the ANN learning phase. Target of this work is to achieve fast-prototyping, small, low-power and cost-effective implementation of ANNs to be employed directly on the sensing nodes of IOT (i.e. Edge Computing). The performance of so- implemented ANNs is assessed for two real applications, namely hand movement recognition based on electromyographic signals and handwritten character recognition. Energy per operation is measured in the FPGA realization and compared with the corresponding ANN implemented on a microcontroller (μC) to demonstrate the advantage of the FPGA based solution.



Standards related to Vhdl

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