What Is Verilog?

Verilog is a hardware description language (HDL) used to model, simulate, and synthesize digital electronic systems. Unlike software programming languages that describe computational procedures, Verilog describes the structure and behavior of hardware circuits, representing both the logical function of a design and its physical implementation in gates and registers. It was originally developed at Gateway Design Automation in 1984 and subsequently submitted to IEEE, which standardized it as IEEE 1364-1995. Later revisions produced IEEE 1364-2001 and IEEE 1364-2005, the current formal specification, before the language was merged into the unified SystemVerilog standard IEEE 1800. Verilog is used throughout the semiconductor design flow, from early architectural modeling to gate-level netlists ready for fabrication.

Verilog and its companion language VHDL, standardized by IEEE as IEEE 1076, are the two dominant HDLs in industry. Verilog is generally preferred in North American and Asia-Pacific design teams for its concise C-like syntax, while VHDL sees more use in European and defense applications. Both languages allow designers to describe hardware at multiple levels of abstraction, enabling large teams to work on different portions of a design before integrating them.

Language Structure and Abstraction Levels

A Verilog design is organized as a hierarchy of modules. Each module defines input and output ports, internal signals, and behavioral or structural descriptions of how inputs map to outputs. Verilog supports three levels of abstraction: behavioral, which uses procedural constructs similar to programming statements; register-transfer level (RTL), which describes data paths and control logic in terms of registers and combinational logic; and gate-level, which represents circuits as interconnected primitive gates. RTL is the most common abstraction for synthesis: a designer writes RTL Verilog and a synthesis tool maps it automatically to a technology library of standard cells or FPGA primitives. The language uses a four-valued logic system with states 0, 1, X (unknown or uninitialized), and Z (high-impedance), reflecting the physical realities of bus-sharing and tri-state drivers in real circuits. The IEEE Standards Association page for IEEE 1364 describes the formal scope of the language as supporting "the development, verification, synthesis, and testing of hardware designs" in a machine-readable and human-readable format.

Simulation and Verification

Verilog includes a discrete-event simulation model in which signal changes propagate through the design according to specified propagation delays. Testbenches, written in Verilog or the more expressive SystemVerilog, apply stimulus to the design under test and monitor outputs against expected values. The simulator schedules events on a time-ordered queue and resolves conflicts according to the language's stratified event scheduling semantics, which distinguish combinational feedback from sequential clocked logic. SystemVerilog, standardized as IEEE 1800, extends Verilog with object-oriented programming constructs, assertions, coverage directives, and constrained-random stimulus generation. These additions form the basis of the Universal Verification Methodology (UVM), the industry-standard framework for functional verification of complex integrated circuits and system-on-chip designs.

Synthesis and Place-and-Route

Logic synthesis translates RTL Verilog into a gate-level netlist by mapping RTL constructs to cells from a target library, such as a foundry standard-cell library for application-specific integrated circuits (ASICs) or the configurable logic blocks of an FPGA. Synthesis tools optimize the netlist for timing, area, and power, subject to constraints specified by the designer. Timing constraints, typically provided in Synopsys Design Constraints (SDC) format, define the required setup and hold times at each flip-flop boundary. After synthesis, place-and-route tools physically arrange the gates on the chip floor plan and route metal connections between them. The resulting layout undergoes physical verification, including design rule checking (DRC) and layout versus schematic (LVS) comparison, before being submitted to a semiconductor foundry as GDSII data. The full flow, from RTL Verilog to tape-out, is the central workflow of digital IC design as practiced at companies and research institutions worldwide.

Applications

Verilog has applications in a range of fields, including:

• ASIC design for consumer electronics, networking, and mobile devices
• FPGA-based prototyping and production in aerospace and telecommunications
• System-on-chip integration for embedded processors and digital signal processors
• Hardware security research including side-channel analysis and hardware Trojans
• High-performance computing accelerators and custom AI inference chips
• Educational platforms for digital logic and computer architecture courses