What Are Tunnel Transistors?

Tunnel transistors, formally known as tunneling field-effect transistors (TFETs), are three-terminal semiconductor devices that control current flow through quantum mechanical band-to-band tunneling rather than through the thermal injection of carriers over a potential barrier. In a conventional metal-oxide-semiconductor field-effect transistor (MOSFET), the subthreshold slope, which sets how sharply the transistor turns on, is limited by Boltzmann statistics to a minimum of 60 millivolts per decade at room temperature. TFETs circumvent this limit by using gate voltage to modulate the width of a tunneling barrier between source and channel, enabling subthreshold slopes below 60 mV/decade and allowing the supply voltage to be reduced substantially while maintaining acceptable on-state current. The result is a device architecture suited to extremely low power integrated circuits where the static and dynamic energy consumption of conventional CMOS has become the binding constraint.

Interest in tunnel transistors intensified in the 2010s as technology roadmaps confronted the difficulty of reducing supply voltage below roughly 0.7 V in bulk CMOS. A Nature paper by Ionescu and Riel established that tunnel field-effect transistors as energy-efficient electronic switches could theoretically achieve a 100-fold reduction in power consumption over CMOS if their on-current density could be brought to practical levels, framing the engineering challenge that has driven TFET research since.

Band-to-Band Tunneling and Operating Principle

In a TFET, the source is doped opposite in polarity to the channel and drain, forming a p-i-n structure in the off state. In an n-type TFET, the source is p+ doped and the drain is n+ doped with an intrinsic or lightly doped channel between them. With zero gate voltage, the misalignment of the valence band in the source and the conduction band in the channel blocks carrier flow; the device is off. As gate voltage increases, the channel band bends, bringing the source valence band into alignment with the channel conduction band. Once the alignment is sufficient, electrons tunnel through the thin barrier from source to channel, producing drain current. The steepness of this turn-on transition is set by the sharpness of the band edge and the tunneling probability, not by the Fermi-Dirac distribution tail, which is the mechanism that breaks the 60 mV/decade limit. Research on TFET for ultra-low power applications documents measured subthreshold slopes below 30 mV/decade in optimized device structures.

Device Structures and Materials

The primary materials challenge for TFETs is achieving simultaneously high on-current and steep subthreshold slope, which requires a thin tunneling barrier, a narrow bandgap at the source junction, and abrupt doping profiles. Silicon TFETs suffer from low on-current because silicon's relatively large bandgap produces a thick tunneling barrier. III-V compound semiconductors such as InGaAs, InAs, and GaSb offer narrower bandgaps and light carrier effective masses that increase tunneling probability dramatically. Heterojunction TFETs, which pair a narrow-bandgap p+ source with an n-type III-V channel, combine high tunneling current with gate electrostatic control. Nanowire and two-dimensional material (graphene, MoS2, black phosphorus) TFETs exploit quantum confinement and atomically thin body structures to further improve gate control and reduce off-state leakage, as surveyed in MDPI Micromachines' review of TFET materials, structures, and applications.

Challenges and Integration

The main obstacles to TFET adoption are on-current density, which remains one to two orders of magnitude below that of CMOS at equivalent supply voltage, and the difficulty of integrating III-V or two-dimensional materials into silicon manufacturing lines. Ambipolar conduction, where the drain can also act as a tunneling source under opposite-polarity bias, creates off-state leakage that must be suppressed through asymmetric doping or gate work function engineering. Hybrid TFET-CMOS circuits, in which TFETs handle leakage-sensitive sleep-mode logic while CMOS handles high-speed paths, represent a near-term integration path that avoids requiring TFETs to match CMOS at all performance points.

Applications

Tunnel transistors have applications in a wide range of disciplines, including:

• Ultra-low power logic for implantable medical devices and IoT sensors
• Near-threshold computing in mobile and wearable electronics
• Steep-slope switches in energy-efficient memory and sensor interfaces
• Terahertz and millimeter-wave circuits exploiting negative differential resistance
• Cryogenic quantum computing control electronics requiring minimal heat dissipation