What Is Timing Jitter?

Timing jitter is the deviation of a clock or data signal's transitions from their ideal, uniformly spaced positions in time. In an ideal periodic signal, each rising or falling edge occurs at exactly the interval specified by the nominal frequency. In a real signal, thermal noise, power supply fluctuations, substrate coupling, and imperfect circuit elements all cause those edges to arrive slightly early or slightly late. The resulting spread in edge timing constitutes timing jitter, and its magnitude sets fundamental limits on the performance of data converters, serial communications links, phase-locked loops, and any system that depends on precise timing references. The topic sits at the intersection of circuit design, statistical signal processing, and metrology.

Jitter and phase noise are two representations of the same underlying phenomenon. Phase noise describes the spectral distribution of phase fluctuations and is measured in decibels relative to the carrier per hertz (dBc/Hz), while jitter is the time-domain integral of phase noise over a specified frequency band. Translating between the two requires knowledge of the bandwidth over which the integration is performed.

Sources of Jitter

Jitter originates from multiple mechanisms, and distinguishing them is important for mitigation. Thermal noise in resistances and active devices produces random phase perturbations that follow a Gaussian distribution, contributing what is called random jitter (RJ). Random jitter is unbounded in theory and its root-mean-square value grows with measurement time. Deterministic jitter (DJ), by contrast, is bounded and predictable; it arises from specific, identifiable causes including periodic supply noise, crosstalk from aggressor signals, duty-cycle distortion, and data-dependent patterns in high-speed serial links. The peak-to-peak amplitude of deterministic jitter is fixed by the coupling mechanism and can be reduced by circuit and layout countermeasures. Substrate bounce in digital ICs and electromagnetic interference from external sources add additional correlated contributions.

Types and Metrics

The SiTime application note on clock jitter definitions and measurement methods defines the standard metrics used in the industry. Period jitter is the deviation of each cycle period from the nominal value, sampled across many cycles; it is the metric most directly relevant to setup and hold timing in digital circuits and is standardized in JEDEC Standard 65B. Cycle-to-cycle jitter measures the change in period between adjacent cycles and is sensitive to high-frequency perturbations. Time interval error (TIE) tracks the accumulated phase offset from a perfect reference edge over the entire observation, and its peak-to-peak range is the maximum time interval error (MTIE). Phase jitter, obtained by integrating the phase noise spectrum from an upper frequency limit down to a lower offset, is the preferred metric for RF and mixed-signal applications. The IEEE paper on clock jitter compensation in high-rate ADC circuits analyzes how jitter-induced noise floors limit analog-to-digital conversion accuracy as sample rates approach gigasamples per second.

Measurement and Mitigation

Oscilloscopes with jitter analysis software, spectrum analyzers, and dedicated phase noise analyzers are the primary instruments for jitter measurement. Histogram methods accumulate thousands of edge arrivals relative to a reference to estimate the probability density of jitter, separating the Gaussian random component from bounded deterministic components. In circuit design, jitter is minimized by using differential signal paths that reject common-mode supply noise, by filtering PLL reference inputs, by using low-noise voltage regulators for oscillator supply pins, and by careful shielding of sensitive timing nodes from aggressor signals.

Applications

Timing jitter is a performance-limiting factor in a range of systems, including:

• High-speed data converters, where aperture jitter directly sets the achievable signal-to-noise ratio at a given sample rate
• Serial communications standards such as PCIe, USB, and 100GBASE-R Ethernet, where jitter budgets are allocated across transmitter, channel, and receiver
• Optical communication systems, where clock recovery circuits must track jitter within tight masks specified by ITU-T standards
• Frequency synthesizers in wireless transceivers, where integrated phase noise determines receiver sensitivity and transmitter spectral purity