What Are Switched Capacitor Networks?

Switched capacitor networks are interconnected arrangements of capacitors and electronically controlled switches that transfer charge between nodes under clock control to synthesize precise analog functions. Unlike passive RC networks, where resistor values set frequency and gain characteristics, switched capacitor networks rely on capacitor ratios and clock frequency to determine their transfer functions. This dependence on ratios rather than absolute component values is the defining property of the approach: capacitor ratios in CMOS processes can be matched to within a fraction of a percent, while absolute capacitance and resistance values vary by 10 to 20 percent across a wafer.

The network concept draws on classical circuit theory, including nodal analysis, z-transform signal flow graphs, and equivalent impedance substitution. Researchers at Bell Laboratories and Columbia University formalized equivalent circuit methods for switched capacitor networks in the late 1970s, establishing the analytical framework that CMOS mixed-signal designers still use today.

Charge Transfer and Equivalent Impedance

The fundamental building block in a switched capacitor network is the two-phase switched capacitor: a capacitor C that connects during one clock phase to a source node and during the complementary phase to a destination node. Over one clock period T, the network transfers a charge Q equal to C times the voltage difference between the two nodes. This behavior is equivalent to a resistor of value T/C, or 1/(fC) where f is the clock frequency, a substitution that allows the entire resistor vocabulary of analog circuit design to be realized with capacitors and switches.

The analysis of switched capacitor networks using driving-point signal flow graphs provides a systematic method for deriving z-domain transfer functions from network topology, treating each switched branch as a discrete-time signal path with defined phase relationships.

Network Topologies

Switched capacitor networks are organized around operational amplifiers that prevent charge sharing errors between stages. In a unity-gain sampler, a capacitor samples the input during one phase and connects across the amplifier feedback path during the next, transferring the sampled voltage without loading the source. In a multiply-by-two topology, two matched capacitors sample in parallel and discharge in series through the amplifier, doubling the output voltage with an accuracy that depends only on the matching of the two capacitors.

Ladder and biquad filter topologies replace the resistors of passive LC ladder prototypes with switched capacitor equivalents, producing band-limited frequency responses whose pole locations track the clock frequency. This tunability is exploited in programmable filter banks and in phase-locked loop components where the loop bandwidth adjusts with an external clock reference. The equivalent circuit framework from the Bell System Technical Journal laid the foundation for systematic network synthesis by mapping each switch-capacitor branch to a linear two-port model.

Noise and Dynamic Range

Thermal noise in switched capacitor networks arises from the resistance of the MOS switches during the sampling interval. The total integrated noise power on a sampled capacitor is kT/C, independent of switch resistance, a result known as the kT/C noise floor. Increasing capacitor size reduces noise but increases die area and power consumption, so capacitor sizing is a central trade-off in network design.

The Analog Devices university course on switched capacitor fundamentals describes how parasitic capacitances at switch nodes introduce charge injection errors that designers mitigate through bottom-plate sampling, correlated double sampling, and fully differential topologies.

Applications

Switched capacitor networks have applications in a range of fields, including:

• Precision analog filters in audio codecs and telephone line interfaces
• Successive approximation and sigma-delta analog-to-digital converters
• Sample-and-hold and track-and-hold circuits in data acquisition systems
• Charge pump voltage converters and regulated power circuits
• Sensor interface circuits requiring matched gain and offset cancellation