What Are Split Gate Flash Memory Cells?

Split gate flash memory cells are a class of non-volatile semiconductor memory devices that merge a floating-gate storage transistor with a select transistor into a single compact structure. Unlike conventional stacked-gate flash cells, which place a control gate directly over the floating gate, the split gate design positions the control or select gate adjacent to and partially over the floating gate, dividing the channel region between two distinct gate regions. This configuration addresses key reliability problems found in standard flash cells, including over-erase, high programming current, and poor data retention under extended cycling.

The architecture emerged from industry efforts in the 1990s to produce embedded non-volatile memory compatible with standard CMOS logic processes. Because the select gate always controls a portion of the channel, the cell cannot be fully depleted during erase, which eliminates the over-erase failure mode that can render stacked-gate cells conductive even when they should read as erased.

Cell Structure and Gate Arrangement

A typical split gate cell contains four functional regions: a floating gate, a select gate, a control gate, and an erase gate. The floating gate is a polysilicon island insulated on all sides by dielectric, which stores charge to represent a programmed state. The select gate sits alongside the floating gate and controls conduction in the portion of the channel it covers. In the most common commercial variants, the erase gate is positioned over the source region and couples strongly to the floating gate edge, enabling efficient poly-to-poly Fowler-Nordheim tunneling during erase operations. Multiple generations of embedded flash technology, including products manufactured at 65 nm and 28 nm ground rules, retain this four-terminal arrangement while shrinking the physical dimensions, as detailed in IEEE Xplore publications on scaling split-gate flash technology to 28 nm embedded flash nodes.

Programming and Erase Mechanisms

Programming is accomplished through source-side injection (SSI), a hot-electron mechanism that injects electrons from the channel into the floating gate near the source junction. SSI requires lower program currents than the channel hot-electron injection used in conventional flash cells because it exploits both the lateral and vertical electric fields at the floating gate edge simultaneously. Erase is performed by Fowler-Nordheim tunneling from the floating gate to the erase gate, a poly-to-poly coupling that operates efficiently at relatively low voltages and does not stress the thin tunnel oxide under the channel. Together, these mechanisms give split gate cells higher endurance over program-erase cycling than stacked-gate alternatives. Analysis of hot-electron programming efficiency in 40 nm split gate cells is examined in depth in IEEE Xplore work on hot-electron programming in advanced split-gate flash memory.

Three-Dimensional and Neuromorphic Extensions

Recent research has extended split gate designs into three-dimensional structures to increase bit density without shrinking lithographic feature sizes. A semicircular 3D variant demonstrated the ability to store more than four bits per cell (quad-level cell operation) by stacking the split gate structure vertically, as reported in IEEE Xplore research on 3D semicircular split-gate flash memory cells. A separate line of work has applied the analog conductance properties of split gate cells to neuromorphic computing, where the cell's ability to be programmed to many intermediate charge states makes it suitable for representing synaptic weights in hardware neural networks.

Applications

Split gate flash memory cells have applications in a range of fields, including:

• Automotive microcontrollers, where high endurance and reliability over temperature are mandatory
• Smartcard and secure element chips requiring embedded non-volatile storage
• Microcontroller units (MCUs) for IoT devices needing code and parameter storage
• Neuromorphic computing hardware using analog memory arrays as artificial synapses
• Industrial embedded systems requiring in-system reprogrammable firmware storage