What Is Silicidation?

Silicidation is a semiconductor fabrication process in which a metal thin film is reacted with silicon at elevated temperatures to form a metal silicide at the interface. The resulting silicide layer has significantly lower electrical resistivity than doped silicon, making silicidation a standard technique for reducing contact and gate resistance in integrated circuits. The process is applied to the source, drain, and gate regions of transistors as device geometries shrink below the point where doped silicon contacts alone can provide acceptable resistance.

The discipline draws on thin-film physics, solid-state chemistry, and process integration engineering. The choice of metal, annealing temperature, ambient atmosphere, and silicon substrate orientation all influence the phase composition, morphology, and electrical properties of the silicide formed. Titanium, cobalt, and nickel are the three metals most widely used in production CMOS processes, with nickel silicide (NiSi) now dominant at the 65 nm node and below.

Silicide Formation Mechanisms

Metal silicides form through solid-state diffusion reactions. When a metal film deposited on silicon is subjected to rapid thermal processing, atoms at the metal-silicon interface react to nucleate silicide grains. The dominant diffusing species, whether metal or silicon atoms, depends on the specific metal system. In nickel silicide formation, nickel is the dominant diffuser; it begins reacting with silicon at temperatures as low as 200°C, first forming Ni₂Si, then the low-resistivity NiSi phase, and finally the high-resistivity NiSi₂ phase at temperatures above approximately 750°C.

The challenges of nickel silicidation in advanced CMOS technologies include NiSi-Fang encroachment defects, where nickel diffuses along substrate defects and creates unpredictable silicide morphology. Managing the thermal budget to stabilize the NiSi phase without converting to NiSi₂ is a central process control challenge.

Self-Aligned Silicide (Salicide) Process

The self-aligned silicide process, commonly called salicide, was developed in the mid-1980s to automate the patterning of silicide to only the active silicon areas. In the salicide sequence, a metal is blanket-deposited over the wafer after the gate and spacer structures are in place. The first rapid thermal anneal reacts metal with exposed silicon on the gate and source/drain areas. Metal that sits on the oxide spacers and field oxide does not react. A selective wet etch then removes the unreacted metal, leaving silicide only where it is needed. A second anneal converts the silicide to its lowest-resistivity phase.

The nickel versus cobalt silicide comparison for sub-50 nm CMOS illustrates the tradeoffs: cobalt disilicide (CoSi₂) offers excellent thermal stability but high stress and narrow process windows on small silicon contacts, while NiSi offers lower sheet resistance and better scaling but requires tighter temperature control to avoid phase conversion.

Scaling Challenges and Advanced Substrates

As device dimensions shrink below 22 nm, silicidation engineering becomes more complex. The contact volume available for silicide formation decreases, requiring tighter control of intrinsic contact resistivity, with targets below 5×10⁻⁹ Ω·cm² for advanced nodes. The transition from planar to three-dimensional transistor architectures, including FinFETs and nanowire devices, introduces geometrical constraints that affect how uniformly the silicide can form on fin surfaces and narrow gate poly lines.

Silicon-germanium (SiGe) source/drain regions, introduced to strain the channel and improve carrier mobility, interact differently with nickel than pure silicon does, producing mixed NiSiGe phases whose resistivity and morphology require dedicated process optimization. The IET Silicide Technology for Integrated Circuits reference provides a detailed treatment of these process integration issues across multiple silicide systems.

Applications

Silicidation has applications in a wide range of fields, including:

• Source and drain contact resistance reduction in CMOS transistors
• Gate electrode sheet resistance reduction in polysilicon gate stacks
• Local interconnect formation in SRAM bitcells
• Ohmic contact formation in bipolar and BiCMOS processes
• Low-resistance contacts in power semiconductor devices