SDRAM

What Is SDRAM?

Synchronous dynamic random-access memory (SDRAM) is a type of dynamic RAM in which the memory interface is synchronized to an external clock signal shared with the host processor bus. Unlike earlier asynchronous DRAM designs that operated on their own internal timing, SDRAM coordinates its read and write operations to the rising edge of the system clock, allowing the memory controller to pipeline requests and achieve higher sustained bandwidth. SDRAM became the dominant form of main memory in personal computers and workstations during the late 1990s and has since evolved through successive generations of double data rate (DDR) variants.

SDRAM draws on the foundational principles of dynamic memory, where each bit is stored as a charge on a capacitor cell that must be periodically refreshed. The synchronous interface adds a finite state machine within the device that accepts commands, manages bank activation, and controls burst transactions without requiring the host to track individual timing signals. This architectural shift was instrumental in enabling the memory bandwidths required by increasingly parallel processor pipelines.

Memory Architecture and Internal Operation

SDRAM is organized into banks, rows, and columns. A memory access begins with a row activation command (RAS) that opens a specific row into a sense-amplifier array, followed by a column access command (CAS) that selects the data within that row. The interval between these two commands, the CAS latency, is one of the primary parameters that characterizes device performance and is specified in clock cycles rather than nanoseconds. Burst mode allows the controller to read or write a contiguous block of columns after a single CAS command, making SDRAM well suited to cache-line fills, which are the dominant access pattern in general-purpose processors. The JEDEC DDR SDRAM standard JESD79 defines the timing parameters, command encoding, and electrical interface for original DDR devices, covering devices from 64 Mb to 1 Gb in x4, x8, and x16 configurations.

DDR Evolution

The transition from single data rate SDRAM to double data rate (DDR) SDRAM in the early 2000s doubled peak bandwidth by transferring data on both the rising and falling edges of the clock. Subsequent generations compounded this improvement: DDR2 raised the bus frequency while lowering operating voltage to 1.8 V; DDR3 reduced voltage further to 1.5 V and introduced prefetch buffering that widened the internal data path; DDR4 extended the standard to speeds above 3.2 Gbps per pin at 1.2 V. The JEDEC DDR4 SDRAM standard JESD79-4 defines the minimum requirements for DDR4 devices from 2 Gb to 16 Gb, specifying the bank group architecture that reduces the effective CAS latency at high clock frequencies. DDR5, standardized in 2020, doubled the burst length to 16, added on-die ECC, and introduced voltage regulators integrated directly on the module.

Performance and System Integration

System designers select SDRAM based on four interrelated parameters: clock frequency, CAS latency, memory bandwidth (the product of bus width and transfer rate), and capacity per module. High-bandwidth memory (HBM), a derivative that stacks multiple DRAM dies connected through silicon vias, was introduced by JEDEC in 2013 and delivers bandwidth an order of magnitude beyond conventional DDR modules by placing memory directly adjacent to the processor die. The JEDEC main memory technology overview provides a roadmap of active standards from DDR4 through HBM3, reflecting the sustained demand for memory bandwidth in compute-intensive workloads.

Applications

SDRAM has applications across a broad range of computing systems, including: