What Is Placement?

Placement is a stage in the physical design flow of very large scale integration (VLSI) circuits in which each cell or logic block of a synthesized netlist is assigned a physical location on the silicon die. The quality of placement determines the lengths of the interconnecting wires, the timing performance of critical paths, and the congestion distribution that the subsequent routing step must navigate. Because billions of transistors must be arranged within a fixed die area while satisfying timing, power, and density constraints, placement is one of the most computationally demanding problems in electronic design automation (EDA). It is formalized as an NP-complete combinatorial optimization problem, and practical solutions rely on heuristic and analytical algorithms that trade solution quality for tractable runtime.

Placement follows floorplanning, in which major blocks and macros are positioned at a coarse level, and precedes detailed routing, in which the actual wire geometries are determined. The two-stage structure of global placement followed by detailed placement, and then routing, reflects the hierarchy of the problem: global placement minimizes a smooth proxy for wire length while allowing cell overlaps, and detailed placement removes overlaps by local perturbation while preserving the global result.

The Placement Problem

The objective of standard-cell placement is to assign (x, y) coordinates on the routing grid to each cell in the netlist so that the estimated total wire length, a proxy for delay and power, is minimized subject to constraints on cell density, timing, and routability. Total half-perimeter wire length (HPWL) is the most common objective because it correlates with routable wire demand and can be computed efficiently. A foundational survey of VLSI cell placement techniques, published in ACM Computing Surveys, catalogs the algorithmic landscape from partitioning-based methods through analytical formulations. The placement problem is complicated by the presence of large pre-placed macros such as memory arrays and analog blocks, which divide the standard-cell region into irregular sub-regions and create obstacles that the placement tool must route cells around. A 2024 ACM symposium paper on challenges in floorplanning and macro placement for modern SoCs examines how growth in macro count is outpacing the ability of classical placement algorithms to close timing automatically.

Placement Algorithms

Three families of algorithms dominate modern placement tools. Simulated annealing, used prominently in the TimberWolf tool of the 1980s, perturbs cell positions iteratively and accepts uphill moves with a probability that decays as a temperature schedule, escaping local minima to find globally good solutions. Its main limitation is runtime: the number of moves required to converge scales poorly with circuit size. Analytical placement, now the prevailing approach in commercial tools, minimizes a convex smoothing of HPWL using gradient-based optimization and then employs spreading operations to eliminate cell overlap. The SimPL algorithm, described in Communications of the ACM, exemplifies this class by alternating between a lower-bound optimization that ignores overlap and an upper-bound legalization step that enforces it, iterating until the two bounds converge. Reinforcement learning and other machine learning methods are an active area of research for macro placement, where the discrete and combinatorial nature of the problem makes gradient-based methods less direct.

Routing and Post-Placement Optimization

Placement and routing are tightly coupled: a placement that creates routing congestion hotspots may be globally optimal in wire length but physically unroutable. Placement tools therefore incorporate congestion estimation, modeling the die as a grid of routing tiles and predicting demand against available wire tracks. Timing-driven placement weights net criticality in the objective function, allocating shorter wire paths to timing-critical connections before routing. After initial routing is complete, engineering change orders (ECOs) may require local cell moves to fix timing violations without disturbing the bulk of the completed routing.

Applications

Placement techniques are applied across a wide range of digital and mixed-signal design domains, including:

• Custom ASIC design for mobile processors, networking chips, and AI accelerators
• Standard-cell physical implementation of FPGAs and programmable logic
• Memory compiler layout for SRAM and register files
• Mixed-signal SoC design integrating analog macros with digital logic
• PCB component placement for high-speed digital and RF circuit boards