What Is Physical Design?

Physical design is the stage in the semiconductor design flow that transforms a synthesized logical netlist into a geometrically defined layout ready for fabrication on silicon. Where logic synthesis maps a hardware description to gates and flip-flops, physical design assigns those elements to precise positions on a chip and connects them with metal wires across multiple routing layers. The discipline draws on computational geometry, combinatorial optimization, graph theory, and device physics, and it sits at the boundary where electrical engineering and computer science meet the constraints imposed by the manufacturing process.

Physical design encompasses integrated circuit layout, the actual geometric representation of transistors, contacts, metal interconnects, and vias that a photolithographic process will pattern onto a silicon wafer. The discipline has grown in complexity as feature sizes have shrunk below 10 nanometers, because at these scales wire resistance, capacitance, and process variation become first-order determinants of circuit performance.

Design Flow and Floorplanning

The physical design flow begins with floorplanning, in which large functional blocks, memory macros, input-output pads, and power distribution structures are assigned to regions of the chip. Floorplan quality has a direct and lasting effect on timing, power, and area: a poor floorplan forces long wires between communicating blocks, degrading signal delay and increasing dynamic power dissipation. Power planning, which establishes the grid of supply rails that distributes voltage across the die, is typically completed during floorplanning because the number and width of power stripes must be determined before standard cells can be placed. The IEEE Xplore digital library hosts extensive literature on floorplanning algorithms and power grid analysis methods.

Placement and Routing

Placement positions the standard cells, which are the pre-characterized logic gates and flip-flops from the cell library, within the regions defined by the floorplan. Modern placers use quadratic or analytical methods to minimize a cost function that combines wire length, timing criticality, and routing congestion. Once placement is legalized, a global router partitions the chip into routing tiles and assigns nets to layers and regions, followed by detailed routing that generates the final geometric wire shapes. Clock tree synthesis, which inserts buffers and balances arrival times across all clock destinations to within tens of picoseconds, is interleaved with placement and routing because clock skew is a major limiting factor in high-speed design. Commercial tools from companies including Synopsys and Cadence automate these steps, as described in ACM publications on VLSI physical design automation.

Physical Verification

Physical verification confirms that the completed layout complies with the foundry's design rule check (DRC) requirements and that its electrical connectivity matches the original netlist through layout-versus-schematic (LVS) checking. DRC rules govern minimum wire widths, spacing between conductors, enclosure requirements for vias, and many other geometric constraints derived from the limits of the photolithographic process. At advanced nodes, additional checks including optical proximity correction (OPC) and lithography-process co-optimization (LPCO) are applied to compensate for the wave-optics effects that distort patterns at sub-wavelength feature sizes. Timing sign-off, performed with static timing analysis (STA) tools, verifies that every combinational path in the design meets its timing constraints under all specified process, voltage, and temperature corners. The NIST VLSI standards and measurements program provides reference data supporting the measurement science underlying physical verification.

Applications

Physical design has applications in a wide range of fields, including:

• Microprocessor and system-on-chip (SoC) design for computing and mobile devices
• Application-specific integrated circuits (ASICs) for networking, storage, and AI accelerators
• Memory chip layout for DRAM, SRAM, and NAND flash
• Mixed-signal and radio-frequency integrated circuit design
• Automotive and aerospace electronics requiring high reliability and radiation tolerance