What Are MONOS Devices?

MONOS devices are a class of nonvolatile semiconductor memory cells built on a metal-oxide-nitride-oxide-silicon stack, in which charge is stored within discrete trap sites in a silicon nitride layer rather than in a conductive floating gate. The acronym reflects the physical layer sequence: a metal control gate sits above a tunneling oxide, a charge-trapping nitride, a blocking oxide, and a silicon substrate below. This architecture places MONOS in the broader family of charge trap flash (CTF) memory, alongside the closely related SONOS variant in which a polysilicon gate replaces the metal layer.

MONOS technology traces its origins to research at Westinghouse Electric Corporation in 1968, predating modern flash memory by more than a decade. The key insight was that a non-conducting dielectric film could store charge just as effectively as a doped semiconductor layer, with the added benefit that isolated trap sites limit the spread of charge loss from individual defects. This structural difference from floating-gate memory has motivated sustained research into MONOS as process nodes shrink below 40 nanometers.

Device Structure and Charge Storage

The core of a MONOS cell is the oxide-nitride-oxide (ONO) trilayer sandwiched between the control gate and the silicon channel. Electrons injected during a write operation become trapped at energy wells distributed throughout the silicon nitride film. Because the nitride is non-conducting, each trapped charge remains electrically isolated from its neighbors; a defect that causes local charge loss does not deplete the entire storage layer. This localized storage also enables a two-bit-per-cell mode in which independent charge packets are programmed near the source and drain ends of the nitride film, effectively doubling the storage density of a single transistor. Research published in IEEE Transactions on Electron Devices on charge injection in MONOS cells has examined how separating the silicon nitride into distinct layers further improves program efficiency.

Programming, Erase, and Retention

Writing data to a MONOS cell uses Fowler-Nordheim tunneling or channel hot-electron injection to push electrons through the thin tunneling oxide into the nitride traps. Erasing reverses the process, pulling charge back out through the same tunneling oxide or injecting holes from the substrate. The blocking oxide above the nitride prevents charge from escaping toward the control gate during erase. A review of high-k dielectric nonvolatile memory published in PMC notes that retention degrades when the silicon nitride film is thinned below roughly 2 nanometers, establishing a practical lower bound on the storage layer at scaled nodes. Hafnium-based high-k alternatives to silicon nitride have been explored to recover the memory window as dimensions shrink.

Scaling and Three-Dimensional Integration

As planar transistors approached their dimensional limits, MONOS cells gained renewed attention because the ONO stack can be deposited conformally over non-planar silicon surfaces. Renesas Electronics demonstrated split-gate MONOS cells built on fin-shaped transistors at 16 and 14 nanometer process nodes, enabling on-chip embedded flash memory for microcontrollers at geometries where floating-gate cells become difficult to fabricate. The fin geometry increases the effective channel width without enlarging the cell footprint, supporting higher endurance and lower operating voltages than equivalent planar designs. These properties also make MONOS a leading candidate for 3D NAND architectures, where memory layers are stacked vertically over a single silicon substrate.

Applications

MONOS devices have applications in a range of fields, including:

• Embedded microcontrollers for automotive and industrial control systems
• Smart cards and secure elements requiring high data retention
• Internet-of-Things edge nodes where low-power nonvolatile storage is essential
• Code storage in consumer electronics such as set-top boxes and wearables
• Radiation-hardened memory for aerospace and defense electronics