What Is Layout?

Layout is the spatial arrangement of functional elements, interconnections, and graphical components within a design, whether that design is an integrated circuit, a printed circuit board, a user interface, or a publication. In electronics and VLSI engineering, layout refers specifically to the process of translating a logical or schematic circuit description into a set of geometric shapes on defined material layers that define the physical construction of a chip or board. The output of this process is a data file, typically in GDSII or OASIS format for integrated circuits or Gerber format for PCBs, that is passed directly to fabrication equipment. Layout quality determines manufacturability, performance, power consumption, and reliability: a logically correct design can fail entirely if its layout violates design rules, creates parasitic capacitances that slow critical paths, or produces electromigration hazards in narrow metal lines.

The discipline is central to electronic design automation (EDA), where software tools assist engineers in placing components, routing signal paths, and verifying that the resulting geometry satisfies both the designer's timing and power objectives and the foundry's process-specific constraints.

Integrated Circuit Layout

Integrated circuit layout transforms a gate-level netlist into a geometrized representation of transistors, contacts, vias, and metal interconnect spanning multiple layers. The back-end design flow, as surveyed in recent work on physical design methodologies from RTL to GDSII, proceeds through a defined sequence: floorplanning establishes the spatial framework by allocating die area to functional blocks and placing I/O pads; power planning distributes supply voltage through rings, stripes, and rail structures; placement positions standard cells within rows to minimize wirelength and timing penalties; clock tree synthesis builds a balanced clock distribution network with controlled skew; and routing establishes signal connectivity through global and detailed routing phases.

Design rule checking (DRC) verifies that all geometric shapes meet the minimum width, spacing, and overlap requirements specified in the process design kit (PDK) for the target technology node. Layout versus schematic (LVS) verification confirms that the geometric connectivity extracted from the layout matches the original netlist. At sub-7 nm nodes, these checks extend to complex multi-patterning constraints and self-aligned via rules that require specialized DRC engines. The ACM/IEEE Design Automation Conference proceedings on AI-driven analog layout synthesis documents how constraint-driven generative frameworks are being applied to automate portions of analog layout that have historically resisted automation because of the sensitivity of transistor performance to device orientation and proximity.

Wiring and Interconnect

Routing is the stage of layout that establishes electrical connections between placed components by assigning paths through the available metal layers. Global routing allocates paths to routing regions at coarse granularity; detailed routing assigns specific tracks and assigns vias, resolving conflicts within the global allocation. At advanced nodes, wire resistance and capacitance contribute significantly to signal delay, and the routing tool must co-optimize wirelength, layer assignment, and via count against a timing budget. Crosstalk between parallel signal wires becomes a functional concern at high frequencies, requiring spacing rules beyond the DRC minimum. Power and ground wiring, handled separately from signal routing, must supply adequate current density across all operating conditions without exceeding electromigration limits set by the foundry.

PCB layout follows analogous principles: component placement affects signal integrity, thermal management, and EMC compliance, while trace routing determines differential pair skew, impedance matching, and return path continuity. The open-source EDA tools and process design kits available for IC layout have expanded access to physical design, enabling university research and small teams to execute full RTL-to-GDSII flows without proprietary tool licenses.

Applications

Layout methods apply across many design and fabrication domains, including:

• ASIC and custom digital IC design for high-performance computing and communications
• Analog and mixed-signal IC design where transistor matching and shielding determine accuracy
• Printed circuit board design for consumer electronics, industrial control, and instrumentation
• MEMS device fabrication, where mechanical and electrical layers must be co-optimized
• Graphic design and document layout tools that adapt spatial placement algorithms for visual media