What Is Latch Up?

Latch up is a destructive failure mode in complementary metal-oxide-semiconductor (CMOS) integrated circuits in which a low-impedance path forms inadvertently between the power supply rails, causing excessive current to flow through the device. The failure arises from parasitic bipolar transistor structures that exist within any CMOS process as a consequence of the n-well and p-substrate arrangement inherent to the technology. Once triggered, the parasitic path can sustain itself indefinitely, producing enough heat to permanently destroy the chip unless external power is removed.

The underlying structure responsible for latch up is a parasitic four-layer PNPN device, functionally equivalent to a silicon-controlled rectifier (SCR) or thyristor. In a standard CMOS process, the n-well resistor and p-substrate resistor form the base resistance elements of two parasitic bipolar transistors, one NPN and one PNP, whose collectors are tied to each other's bases. When a sufficient trigger current flows through either base resistance, positive feedback between the two transistors drives the structure into a low-impedance conducting state. This condition, known as snapback, latches the device and persists as long as the holding current exceeds a minimum threshold.

ESD and Electrical Stress Triggering

Electrostatic discharge is among the most common latch-up triggers in production environments and field use. An ESD event delivers a transient current pulse that can inject minority carriers into the substrate or well, forward-biasing a parasitic junction and initiating the feedback loop. Electrical overstress conditions, such as voltages on signal pins that momentarily exceed the supply rail, produce similar substrate injection. The JEDEC JESD78 standard for IC latch-up testing defines two test methods: a supply overvoltage test applied to power pins and a current injection test of ±100 mA applied to signal pins. Together these procedures evaluate both the supply-side and I/O-side susceptibility of a device and establish pass/fail criteria for production qualification.

Ionizing radiation is an additional trigger relevant to space and military electronics. High-energy particles traversing a CMOS die generate electron-hole pairs along their tracks, depositing enough charge locally to activate the parasitic thyristor. Single-event latch-up (SEL) from heavy-ion or proton bombardment has been a documented reliability concern since the early years of satellite electronics, and radiation-hardened CMOS processes address it through layout and process modifications.

On-Chip Protection and Design Countermeasures

Protection against latch up is addressed at both the process and circuit levels. Guard rings, which are heavily doped diffusion bands placed around n-well and p-substrate regions, collect injected carriers before they reach the parasitic base regions, increasing the trigger threshold substantially. Retrograde well profiles and epitaxial substrates reduce the well sheet resistance, lowering the gain of the parasitic bipolar pair and suppressing the feedback mechanism.

At the circuit level, the placement of n-well ties and substrate ties close to active devices reduces the effective base resistance and raises the holding current above normal operating conditions. ESD protection networks, including clamping diodes from every I/O pad to the supply rails, limit the transient voltage that reaches the core circuitry. A detailed treatment of these device and circuit design approaches for ESD and latch-up protection in advanced CMOS covers the tradeoffs between protection area, capacitance loading, and robustness as process nodes scale below 28 nm.

The ESD Industry Council white paper on latch-up testing practices surveys how different manufacturers apply JESD78 across technology nodes, documenting variation in clamping levels, injection currents, and temperature conditions used in qualification flows.

Applications

Latch up analysis and mitigation apply across a range of design and reliability domains, including:

• CMOS digital logic in consumer electronics where ESD events during handling are common
• Mixed-signal and analog-digital interface circuits exposed to voltage transients on I/O pins
• Power management integrated circuits operating at elevated supply voltages
• Radiation-hardened electronics for satellite, aerospace, and defense systems
• Automotive semiconductor components subject to electrical overstress from load dumps