What Are Junctionless Nanowire Transistors?

Junctionless nanowire transistors (JNTs) are a class of field-effect transistors in which the channel, source, and drain regions share a single uniform doping type and concentration, with no p-n junctions separating them. Conventional MOSFET architectures rely on sharp doping transitions at the source-channel and channel-drain interfaces to control carrier injection; as transistor dimensions shrink below 10 nanometers, achieving the necessary abruptness of those transitions becomes increasingly difficult with ion implantation techniques. The junctionless design sidesteps this fabrication challenge by using a single heavily doped semiconductor nanowire as the active region, relying on the gate's electrostatic control to fully deplete the wire and switch the device off.

The concept was demonstrated experimentally in 2010 by Jean-Pierre Colinge and colleagues using silicon nanowires, reported in a landmark paper in Nature Nanotechnology. That work showed that devices fabricated on a single uniformly doped nanowire exhibited near-ideal subthreshold slopes, low off-state leakage, and full CMOS compatibility, prompting substantial research into junctionless architectures as candidates for transistor scaling below the 5-nanometer node.

Device Physics and Operation

A junctionless transistor operates primarily through bulk conduction rather than the surface channel conduction that characterizes conventional MOSFETs. In the on state, carriers flow through the full volume of the nanowire, not just a thin inversion layer at the dielectric interface. The gate depletes the wire by imposing a potential barrier; when the wire diameter is small enough (typically a few nanometers), the gate can achieve full depletion across the entire cross-section, reducing off-state current to levels comparable to or better than junction-based devices. The threshold voltage is set by the work-function difference between the gate material and the doped silicon, rather than by doping profiles at junctions. Key performance metrics including subthreshold slope, drain-induced barrier lowering (DIBL), and on-to-off current ratio depend critically on the wire diameter, doping concentration, and gate dielectric quality. Design guidelines for these parameters are analyzed in the ScienceDirect article on JNT properties and design guidelines.

Nanowires and Silicon-on-Insulator Substrates

Nanowire geometry is intrinsic to the junctionless design because electrostatic control of the full wire volume requires a channel diameter small enough for the gate's field to penetrate from the surface to the center. Silicon nanowires in the 5-to-20-nanometer diameter range satisfy this requirement for typical gate dielectric thicknesses. Fabrication typically employs either top-down etching of silicon-on-insulator (SOI) wafers or bottom-up growth of crystalline silicon wires. SOI substrates are particularly well suited because the buried oxide layer provides electrical isolation from the substrate, reducing parasitic leakage and simplifying the back-gate contact. Gate-all-around (GAA) geometries, in which the gate dielectric and metal wrap completely around the nanowire, give the strongest electrostatic control and are the architecture toward which current logic process development is directed. Research into alternative doping approaches, including using deliberate dielectric defects in place of impurity doping, is described in a 2025 study published in ACS Nano on junctionless silicon nanowire transistors without impurity doping.

Applications

Junctionless nanowire transistors have applications in a wide range of semiconductor technologies and domains, including:

• Sub-5-nanometer logic transistors in advanced CMOS processes
• Low-power embedded memory and neuromorphic computing circuits
• Biosensors and chemical sensors exploiting surface sensitivity of nanowire geometry
• Radiation-hardened electronics for space and defense applications
• Research platforms for fundamental studies of quantum transport in nanoscale conductors