What Are Interface States?

Interface states are localized electronic energy levels that exist at the boundary between two dissimilar materials, most commonly at a semiconductor-dielectric or semiconductor-metal junction. Unlike the delocalized band states of the bulk crystal, interface states arise from the abrupt termination of the periodic crystal potential, structural defects at the junction, or chemical bonds formed between the two materials at the interface. These states lie within the semiconductor's forbidden energy gap and can trap charge carriers from the bulk, altering the local electrostatic potential, shifting threshold voltages, degrading carrier mobility, and contributing to leakage current. In any device that relies on a semiconductor-insulator interface, the density and energy distribution of interface states are among the most critical parameters for performance and long-term reliability.

The theoretical basis for interface states was established independently by Tamm in 1932 and Shockley in 1939. Tamm showed that an abruptly terminated crystal potential produces localized evanescent states within the band gap. Shockley demonstrated a distinct class of intrinsic surface states that arise from band crossings when two bulk bands of different symmetry invert near a band gap. Experimental verification came in the 1950s and 1960s with the development of the MOS capacitor, which provided a controlled structure for measuring interface state density through capacitance-voltage profiling.

Si/SiO2 Interface States

The silicon-silicon dioxide interface is the most thoroughly studied interface in semiconductor technology. Its importance stems from the central role of the MOS field-effect transistor in integrated circuits. Thermal oxidation of silicon at temperatures above 900 degrees Celsius produces a high-quality interface with state densities typically in the range of 10^10 cm^-2 eV^-1, the lowest achieved for any semiconductor-dielectric pair. These states are predominantly amphoteric traps linked to unsatisfied silicon bonds (Pb centers) at the interface. Post-oxidation hydrogen annealing passivates most of these centers by forming Si-H bonds, reducing the interface state density by an additional order of magnitude. As detailed in ScienceDirect's coverage of electronic states at the silicon-silicon dioxide interface, the energy distribution of remaining states is U-shaped, with peaks near the valence and conduction band edges and a lower density in the mid-gap region.

Interface States in Wide-Bandgap Semiconductors and Silicon-on-Insulator

Silicon carbide (SiC) and gallium nitride (GaN), used in power electronics and radio-frequency devices, exhibit interface state densities two to three orders of magnitude higher than Si/SiO2, primarily because their wider band gaps expose more defect states in the gap and because their oxide formation chemistry is less mature. In SiC/SiO2 structures, near-interface traps within the first few nanometers of the oxide are particularly problematic. As shown in research on near-interface trap density in commercial SiC MOSFETs, roughly 10 percent of channel electrons are captured by these traps on a timescale of hundreds of nanoseconds at typical operating voltages, reducing effective mobility and causing threshold voltage instability. Silicon-on-insulator (SOI) structures face related issues at the buried oxide interface, where a second Si/SiO2 junction below the device layer introduces a back-channel with its own interface state population, requiring separate characterization and passivation strategies.

Measurement and Passivation

Interface state density is most commonly quantified by the capacitance-voltage (C-V) method and the conductance method on MOS capacitors, both of which extract the interface state density as a function of energy position within the band gap. The NIST study on interface traps in NO-annealed SiC MOSFETs illustrates how nitric oxide annealing introduces nitrogen at the SiC/SiO2 interface, partially replacing carbon clusters and reducing the state density sufficiently to enable manufacturable SiC power transistors with acceptable channel mobility.

Applications

Interface states have practical importance across a wide range of fields, including:

• Power electronics, where SiC and GaN MOSFET channel mobility depends directly on interface state passivation at the gate oxide
• CMOS logic scaling, where bias temperature instability linked to interface state generation sets limits on gate dielectric thickness and operating voltage
• Solar cell fabrication, where interface states at the junction reduce open-circuit voltage and require surface passivation layers to meet efficiency targets
• Silicon-on-insulator device design, where back-interface state density influences floating-body and kink effects in partially depleted SOI transistors
• Thin-film transistors for display backplanes, where interface states at the amorphous oxide-dielectric boundary determine subthreshold slope and threshold voltage uniformity