What Are IEEE Computer Architecture Letters?

IEEE Computer Architecture Letters is a peer-reviewed journal of the IEEE Computer Society dedicated to the rapid dissemination of early, high-impact results in computer architecture and related systems areas. The journal publishes concise four-page papers, a format that focuses attention on the central insight of a contribution rather than on exhaustive experimental evaluation. Its scope covers uniprocessor and multiprocessor computer systems, microarchitecture, workload characterization, performance evaluation methodologies, power-aware computing, parallel computing, embedded systems, and cache design. The journal has served the computer architecture research community for over two decades, providing a distinct venue between conference proceedings and long-form transactions articles.

The four-page constraint is a deliberate editorial choice. The computer architecture community has historically relied on annual conferences as its primary venue for timely research exchange, but conference paper deadlines occur only once or twice a year. IEEE Computer Architecture Letters fills the gap by offering archival peer review on a rolling schedule, allowing authors to establish priority and circulate early results without waiting for the next conference cycle.

Scope and Article Format

IEEE Computer Architecture Letters accepts research on processor design, instruction-level parallelism, memory hierarchy, branch prediction, out-of-order execution, and hardware security, among other architecture topics. Papers in the journal are expected to introduce genuinely novel ideas or insights rather than to provide the depth of analysis characteristic of a full conference or transactions paper. The four-page format requires that claims be focused and that experimental support be sufficient to validate the core contribution without attempting to cover all edge cases. Many authors subsequently expand accepted letters into full conference papers with more extensive evaluation, treating the journal as a rapid dissemination step in a longer publication trajectory.

Rapid Review and Publication Process

The journal's review process is structured for speed. The target for first decision is approximately 30 days, considerably faster than either major architecture conferences or transactions journals. Around 85 percent of submissions receive an initial decision within that window. The acceptance rate of approximately 35 percent reflects a balance between accessibility and rigor: the journal accepts papers with ideas it considers genuinely novel while requiring that contributions clear a meaningful technical bar. Papers accepted through IEEE Computer Architecture Letters on IEEE Xplore are made available in early access ahead of issue assembly, reducing the effective lag between acceptance and public availability.

Relationship to the Architecture Research Community

The journal is co-published with the ACM, connecting it to the ACM SIGARCH community that organizes ISCA, the International Symposium on Computer Architecture. This dual-society sponsorship reflects the journal's positioning as a community resource shared between IEEE and ACM members rather than as a property of a single society's publication portfolio. The editorial board was substantially expanded and internationalized in 2025, adding expertise across Europe, Asia, and the Americas to improve review coverage and reduce turnaround time for submissions from across the global architecture research community.

Applications

IEEE Computer Architecture Letters addresses research with applications across hardware design and systems engineering, including:

• Processor microarchitecture design for server, mobile, and embedded platforms
• Memory hierarchy optimization for data-intensive workloads in high-performance computing
• Hardware security mechanisms including memory protection and side-channel defenses
• Power and energy efficiency techniques for data center and edge computing processors
• Simulation methodology and performance modeling for emerging instruction set architectures