What Are Double-Gate FETs?

Double-gate field-effect transistors (DG-FETs) are metal-oxide-semiconductor transistors in which two gate electrodes control the channel from opposite sides of a thin semiconductor body, rather than from a single side as in a conventional planar MOSFET. By placing gates above and below the channel, or on both flanking walls in a vertical fin geometry, the device can modulate carrier density throughout the full thickness of the semiconductor film rather than only near one surface. This dual control substantially suppresses the short-channel effects that limit conventional transistors at gate lengths below roughly 100 nanometers, and it improves the ratio of drive current to leakage current in ways that single-gate bulk silicon designs cannot match.

The concept was first proposed by Sekigawa and Hayashi in a 1984 paper on the XMOS device, and it was further developed through silicon-on-insulator (SOI) substrate research in the late 1980s and 1990s. DG-FETs draw on solid-state physics, semiconductor process engineering, and compact modeling, and their most commercially successful manifestation, the FinFET, has been the dominant transistor architecture in high-performance logic manufacturing since roughly the 22 nm technology node. A PMC review of FinFET technology history and structure covers the evolution from planar DG-FET concepts to the three-dimensional fin structures in production today.

Device Architecture and Electrostatics

The core principle of a double-gate FET is electrostatic volume inversion. In a thin-body device, the depletion region from one gate overlaps with that from the other, so the entire silicon film can be fully depleted even at relatively low gate voltages. This full depletion reduces the capacitive coupling between the drain and the channel that leads to drain-induced barrier lowering (DIBL), one of the most problematic short-channel effects in scaled transistors. With both gates tied together and the body thickness kept below roughly one-third of the gate length, the threshold voltage is controlled primarily by gate geometry rather than channel doping, which simplifies device design and reduces variability from dopant statistical fluctuations.

The silicon-on-insulator substrate plays a key role in the planar DG-FET implementation. The buried oxide layer beneath the thin silicon film isolates the body from the substrate, preventing parasitic conduction paths and making it practical to fabricate a bottom gate beneath the channel. Research on quantum confinement effects in double-gate SOI FinFETs shows that at body thicknesses below 5 nanometers, quantum mechanical confinement raises the effective threshold voltage and modifies the carrier mobility, effects that compact models must account for at the most advanced technology nodes.

Short-Channel Effect Control

Short-channel effects arise because the drain electric field penetrates into the channel region and reduces the gate's ability to control carrier flow. In a double-gate transistor, the two gate electrodes together provide a much stronger coupling to the channel than a single gate, measured by the natural length parameter lambda, which decreases as the body becomes thinner. Simulations and measurements consistently show that the double-gate structure provides the best short-channel behavior among one-gate, two-gate, and gate-all-around configurations at equal channel lengths, enabling reliable operation at gate lengths down to approximately 5 nm when the body is scaled proportionally.

FinFET Fabrication and the Transition to 3D Transistors

The practical challenge with planar double-gate transistors is alignment: the top and bottom gates must be precisely aligned to avoid parasitic capacitances and threshold voltage offsets. The FinFET architecture, patented by Hisamoto and colleagues at Hitachi in the late 1990s and later developed by a Berkeley team, solves this by replacing the flat channel with a narrow vertical fin of silicon, with the gate electrode wrapped around both sides and the top simultaneously. This self-aligned structure eliminated the alignment problem and proved manufacturable in high-volume CMOS fabs. Intel introduced FinFETs at the 22 nm node in 2011, followed by all major foundries at 14 nm and below. Google Patents records the foundational FinFET transistor structure from its original US patent.

Applications

Double-gate FETs have applications in a range of disciplines, including:

• High-performance CPU and GPU logic in consumer and data-center processors
• Low-power SRAM cells in embedded and mobile applications
• RF front-end circuits in 5G and millimeter-wave communication systems
• Radiation-hardened digital circuits for space and defense electronics
• Ultra-low-leakage circuits for IoT edge devices