What Is Deep Level Transient Spectroscopy?

Deep level transient spectroscopy (DLTS) is an electrical characterization technique used to detect, identify, and quantify electrically active defect states located deep within the bandgap of semiconductor materials. These deep-level traps, situated more than a few tenths of an electron volt from the conduction or valence band edges, act as recombination and generation centers that degrade carrier lifetime, leakage current, and device performance. By measuring the capacitance transient that follows a voltage pulse applied to a p-n junction or Schottky diode, DLTS extracts the activation energy, capture cross-section, and concentration of each trap species present in the depletion region.

The technique was introduced by David V. Lang at Bell Laboratories in 1974, who showed that correlating capacitance transients measured at different temperatures with a rate window produces a spectrum with peaks that identify individual trap levels. The method offered a major advance in sensitivity and resolution over earlier capacitance-voltage and current-temperature methods, and it quickly became the standard tool for characterizing radiation damage, ion-implantation-induced defects, and impurity centers in silicon, gallium arsenide, and other compound semiconductors. Work published in IEEE Transactions on Electron Devices has extended the technique to current transient spectroscopy, which measures the current rather than the capacitance signal to access very low trap concentrations.

Measurement Principle

A DLTS measurement is performed on a diode structure maintained under reverse bias, which depletes the semiconductor region of mobile carriers. A majority-carrier pulse briefly forward-biases the device, filling deep-level traps with carriers. When the reverse bias is restored, trapped carriers are thermally emitted back to the band, causing the depletion capacitance to relax toward its equilibrium value with a time constant that depends on temperature and trap emission rate. By sweeping the sample temperature from cryogenic conditions to near room temperature (or beyond) and applying a fixed rate window to the transient signal, each trap level appears as a distinct peak in the DLTS spectrum. The peak temperature, combined with an Arrhenius analysis of emission rates measured at multiple temperatures, yields the trap activation energy with millielectronvolt resolution. Research on first-principles-based defect identification for DLTS has demonstrated how density functional theory calculations can be combined with experimental spectra to assign atomic identities to observed trap signatures.

Instrumentation and System Variants

Standard DLTS systems consist of a cryostat for temperature control, a lock-in amplifier or digital correlator for rate-window filtering, and a capacitance meter operating in the megahertz range. The choice of rate window determines which emission time constants are selected, and multiple rate windows can be applied simultaneously using the Laplace DLTS variant, which resolves closely spaced trap levels that overlap in conventional spectra. High-temperature DLTS (HT-DLTS) systems, designed for measurements up to 1100 K, have been developed specifically for wide-bandgap semiconductors such as silicon carbide and gallium nitride, where deep traps require elevated temperatures for thermal emission. A high-temperature DLTS system developed for wide-bandgap semiconductor defect studies demonstrated characterization of traps as deep as 2.5 eV from the band edge, expanding the technique's reach into materials relevant to high-power and high-frequency electronics.

Applications

Deep level transient spectroscopy has applications in a range of semiconductor research and production contexts, including:

• Characterization of radiation-induced defects in silicon detectors used in high-energy physics experiments
• Quality control of epitaxial layers in gallium arsenide and indium phosphide photonic devices
• Defect engineering in silicon carbide and gallium nitride for power electronics
• Analysis of interface traps at silicon/silicon dioxide boundaries in CMOS process development
• Investigation of recombination centers in silicon solar cells to optimize minority-carrier lifetime