What Is a Complex Instruction Set Computer?

A complex instruction set computer, abbreviated CISC, is a processor whose instruction set architecture provides many instructions, several addressing modes, and individual instructions that perform multi-step operations such as loading an operand from memory, computing on it, and storing the result. Instruction encodings are usually variable in length, and a single instruction can occupy anywhere from one to more than a dozen bytes. The label is retrospective. It was coined only after the reduced instruction set approach appeared as a contrast, and it describes the design philosophy that dominated commercial computer architecture from the 1960s through the early 1980s, exemplified by the IBM System/360, the DEC VAX, the Motorola 68000, and the Intel x86 family.

The design responded to the conditions of its time. Memory was expensive and slow relative to the processor, compilers were weak, and much system software was written in assembly language, so an instruction set that expressed more work per instruction reduced program size and narrowed the gap between machine code and high-level language constructs. Implementing those instructions in microcode, a layer of interpreted control words stored in fast on-chip memory, let architects add capability without redesigning the hardwired control logic for each new operation.

Instruction Set Characteristics and Microcode

Typical CISC features include memory-to-memory arithmetic, orthogonal addressing modes such as indexed, indirect, and auto-increment, instructions that operate on strings or entire procedure call frames, and condition codes set implicitly as a side effect of computation. The VAX carried this furthest, offering polynomial evaluation and queue manipulation as single instructions. Microcoded control made such instructions practical, since each architectural instruction expanded into a sequence of micro-operations that drove the datapath. The cost was that instruction execution time varied widely, decoding was serial because instruction length was not known until part of the opcode had been examined, and pipelining was difficult to apply uniformly.

The Comparison With Reduced Instruction Sets

The critique arrived in 1980 with the Patterson and Ditzel paper The Case for the Reduced Instruction Set Computer, which argued that compilers used only a small fraction of the available instructions, that microcode consumed chip area better spent on registers and caches, and that a simple fixed-length instruction set could be pipelined to a higher clock rate and yield greater throughput despite executing more instructions per program. The argument shaped a generation of designs including MIPS, SPARC, and later ARM. It did not displace CISC in the market, because binary compatibility with an existing software base proved more valuable to customers than architectural elegance.

Modern Implementations

Contemporary processors that expose a CISC instruction set do not execute it directly. The front end decodes each architectural instruction into one or more fixed-format micro-operations that are then renamed, scheduled out of order, and issued to execution units that look much like those of a reduced instruction set machine, with a micro-operation cache absorbing much of the decode cost for hot loops. Measurements reported in Power Struggles, an HPCA 2013 study of contemporary ARM and x86 parts and the extended ISA Wars analysis in ACM Transactions on Computer Systems found that performance and energy differences between the two families track microarchitecture, process technology, and design target rather than the RISC or CISC character of the instruction set itself. The distinction now matters most for decoder complexity, code density, and the effort required to verify the architecture.

Applications

Complex instruction set architectures appear in a range of computing contexts, including:

• Desktop, laptop, and server processors in the x86-64 family
• Legacy mainframe and minicomputer systems maintained for compatibility
• Embedded microcontrollers derived from the Motorola 68000 and 8051 lines
• Binary translation and virtualization layers that emulate one architecture on another
• Compiler backend design, instruction selection, and code density optimization
• Computer architecture education and simulator development