What Are Chiplets?

Chiplets are small, functionally specialized integrated circuit dies designed to be assembled with other dies inside a single package, so that the finished product behaves as one system rather than as a collection of separate components. A chiplet-based processor might place compute cores on one die, memory controllers and I/O on another, and analog or radio circuitry on a third, joined by high-density interconnect on an interposer or organic substrate. This is a departure from the monolithic system on chip, in which every block is fabricated together on one large die in one process node.

The shift is driven by manufacturing economics as much as by architecture. Defect density is roughly constant per unit area, so yield falls sharply as die size grows, and the reticle field of a lithography scanner puts a hard ceiling near 850 square millimeters on how large a single die can be. Splitting a design into several smaller dies raises the yield of each piece and lifts the reticle limit on total silicon area. Disaggregation also lets each function use the process node that suits it. Logic benefits from the newest node, while SRAM, analog, and I/O circuits scale poorly and cost less on a mature node, so mixing nodes within one package saves money without sacrificing logic performance.

Disaggregation and IP Reuse

The idea of a reusable hardware block predates the chiplet, but earlier IP reuse happened at the design-file level, where a licensed block was integrated into a new die and re-verified for each node. Chiplets move reuse to physical silicon: a validated die can be dropped into many products without being re-implemented. DARPA formalized this goal in its Common Heterogeneous Integration and IP Reuse Strategies program, which aimed at a modular design and manufacturing flow with published physical and electrical interface standards, so that dies from different suppliers could be composed with something close to plug-and-play integration.

The practical consequence is a change in where design effort goes. Partitioning becomes a first-order decision, since every cut in the block diagram turns an on-die wire into a die-to-die link with real latency, power, and area cost. Test strategy changes too, because a package built from several dies is only as good as its worst component, which makes known-good-die screening before assembly essential to overall cost.

Die-to-Die Interfaces

A chiplet is useful only if the link between dies is fast and cheap enough in energy terms to substitute for on-die wiring. Parallel interfaces such as Advanced Interface Bus and Bunch of Wires trade many slow, short wires for low energy per bit, while serial interfaces cover longer reaches at higher energy cost. Universal Chiplet Interconnect Express, introduced in 2022, has become the common denominator: it defines a physical layer, a die-to-die adapter, and a protocol layer that carries PCIe and CXL traffic between dies. Reported three-dimensional system-in-package designs using UCIe show the bandwidth density and picojoule-per-bit figures that make cross-die partitioning viable in high-performance parts.

Packaging and Integration Technology

Chiplet assembly depends on packaging that can carry thousands of connections between neighboring dies. Silicon interposers provide fine-pitch routing in a 2.5D arrangement, embedded silicon bridges place a small routing die only where dense connections are needed, and organic substrates with fine redistribution layers offer a cheaper option at coarser pitch. True 3D stacking with hybrid bonding brings pitches into the single-digit micrometer range and stacks cache directly above logic. Each option carries its own thermal and mechanical constraints, since stacked dies trap heat and the mismatch in thermal expansion between silicon, substrate, and mold compound drives warpage and solder fatigue. As industry accounts of the chiplet transition note, packaging has moved from a back-end afterthought to a co-designed part of the architecture.

Applications

Chiplets have applications in a range of fields, including:

• Server and data center CPUs assembled from replicated compute dies
• GPUs and AI accelerators that pair logic dies with stacked high-bandwidth memory
• Networking and switch silicon combining digital logic with high-speed SerDes
• Automotive and industrial controllers mixing mature-node analog with advanced-node compute
• Aerospace and defense systems requiring trusted domestic assembly of mixed-source dies
• RF and mixed-signal front ends integrated alongside digital baseband processing