What Are Capacitance-Voltage Characteristics?

Capacitance-voltage (C-V) characteristics are the measured relationship between the small-signal capacitance of a semiconductor device or structure and the DC bias voltage applied to it. The resulting C-V curve reveals the charge distribution, dielectric quality, and carrier concentration inside the device without destroying it. Because capacitance depends on how charge responds to an incremental voltage perturbation, the shape of the C-V curve encodes detailed information about the semiconductor physics at and near the device junctions.

C-V analysis originated in the study of MOS (metal-oxide-semiconductor) capacitors in the 1960s and has since become a standard tool in semiconductor process development, device physics research, and production monitoring. It draws on solid-state physics, dielectric theory, and precision AC measurement instrumentation.

MOS Capacitor Behavior

The C-V curve of a MOS capacitor divides into three recognizable regimes as the gate voltage sweeps from negative to positive (for a p-type substrate). In accumulation, majority carriers pile up at the oxide-semiconductor interface, and the device presents a capacitance close to the oxide capacitance C_ox. As the voltage increases through the flatband condition and into depletion, a space-charge region forms in the silicon, adding a depletion capacitance in series with C_ox and causing the total capacitance to fall. Further increase of the voltage drives the semiconductor into inversion, where a minority-carrier layer forms at the interface; at low measurement frequencies the inversion charge can follow the AC signal and the capacitance recovers toward C_ox, while at high frequencies (above roughly 1 MHz) it cannot, so the capacitance remains at a minimum set by the maximum depletion width. C-V characterization of MOS capacitors using the 4200A-SCS parameter analyzer from Keithley Instruments details the measurement circuit and interpretation of the three-regime curve.

Extracted Device Parameters

The practical value of C-V measurement lies in the parameters it can extract nondestructively. Oxide thickness is obtained directly from the accumulation-regime capacitance and the gate area. The flatband voltage, which shifts in the presence of fixed oxide charge or mobile ionic contaminants, is located by differentiating the C-V curve and finding the inflection point. The substrate doping concentration is computed from the slope of a 1/C² versus voltage plot in the depletion regime, and spatial doping profiles are derived from differential C-V analysis at multiple frequencies. Threshold voltage, which determines MOSFET turn-on, is read from the onset of strong inversion. These parameters collectively characterize the quality of the gate dielectric and the silicon surface, making C-V measurement indispensable in CMOS process development. The Berkeley textbook chapter on MOS capacitor fundamentals provides derivations connecting each C-V feature to the underlying device physics.

C-V Profiling and Advanced Structures

Beyond the simple MOS capacitor, C-V techniques are applied to p-n junction diodes, Schottky contacts, heterojunctions, and compound semiconductor devices. Dopant profiling by C-V extracts concentration as a function of depth, which is critical for evaluating implant and diffusion process steps. High-k dielectrics used in sub-22 nm CMOS nodes require modified C-V interpretation because quantum-mechanical effects and polysilicon depletion alter the apparent oxide thickness; measurements at multiple frequencies help separate these contributions. Strained semiconductor layers and III-V compound structures each introduce additional C-V features tied to their band alignment and interface state densities. Research methods for C-V analysis of high-resistivity substrates are reviewed in studies accessible through IEEE Xplore.

Applications

Capacitance-voltage characteristics are used across a broad range of contexts, including:

• Gate dielectric characterization in CMOS and high-k metal-gate process development
• Threshold voltage monitoring in transistor manufacturing process control
• Dopant concentration profiling in ion-implanted and epitaxial semiconductor layers
• Interface state density evaluation at oxide-semiconductor junctions
• Schottky barrier height extraction for compound semiconductor devices