What Are Asynchronous Logic Circuits?

Asynchronous logic circuits are digital integrated circuits in which logic gates and storage elements operate on local control signals rather than on a globally distributed clock. Whereas synchronous logic advances through states on a shared clock edge delivered simultaneously to all flip-flops, asynchronous logic circuits use completion signals, handshake protocols, or self-timed delay elements to sequence operations locally. The result is a circuit whose behavior depends on the logical completion of operations rather than the passage of a fixed time interval. Asynchronous logic circuit design is a subfield of IC design that draws on combinational logic theory, formal verification, and timing-hazard analysis.

The motivations for removing the global clock include eliminating clock distribution power and skew, enabling operation across a wide range of supply voltages and process corners, and producing circuits that adapt automatically to actual computation time rather than worst-case timing budgets.

Logic Encoding and Completion Detection

A key challenge unique to asynchronous logic design is signaling when a combinational operation is complete. In synchronous logic, the clock period is set long enough to accommodate the worst-case gate delay path; completion is implicit. In asynchronous logic, completion must be explicit. The most common approach is dual-rail encoding: each logical bit is represented by two wires, and a valid data value is indicated by one wire being high and the other low (encoding a 0 or 1), while both wires low (the spacer state) indicates that no valid data is present. A completion detection circuit observes all output wires and asserts a done signal only when every output bit is encoded in a valid, non-spacer state. This technique is foundational to quasi-delay-insensitive (QDI) circuits, the most rigorously correct class of asynchronous logic, whose operation is independent of gate and wire delays. The Portland State Asynchronous Research Center's circuit design reference covers dual-rail encoding and the C-element, the basic storage primitive in QDI pipelines.

Synthesis and IC Design Flow

Designing asynchronous logic circuits requires IC design tools and methodologies that differ substantially from synchronous flows. Standard synthesis tools map hardware description language (HDL) to synchronous flip-flop-based netlist; asynchronous synthesis requires specification languages and compilers that preserve concurrency and generate handshake-correct netlists. Research languages such as Balsa and CHP (Communicating Hardware Processes) allow designers to specify asynchronous behavior at a high level, with compilation to gate-level implementations. Layout and place-and-route tools developed for synchronous design can be reused, but the absence of a timing constraint file changes the verification flow: static timing analysis is replaced by handshake protocol verification and timing hazard checks. Research from IEEE Xplore on FPGA implementation of asynchronous circuits using two-phase handshaking illustrates how asynchronous logic circuits have been mapped to reconfigurable hardware, extending asynchronous design beyond custom IC fabrication.

Timing Hazards and Correctness

Asynchronous logic circuits are susceptible to hazards that synchronous circuits tolerate because of the clock's timing window. A static hazard occurs when a combinational circuit momentarily glitches to the wrong value before settling; in a synchronous design, the clock samples after settling, masking the glitch. In an asynchronous circuit, a completion detection circuit that fires on a glitch produces a spurious early-completion signal, propagating an incorrect result. Isochronic forks, wires that branch and whose branches are assumed to have equal delay, are a subtle source of failure in QDI designs: violation of the isochronic assumption causes the circuit to misread which branch received an event first. The EDN overview of asynchronous circuits and power discusses how these design constraints are managed in practice and how they compare with the timing challenges of deep-submicron synchronous IC design.

Applications

Asynchronous logic circuits have applications in a range of IC design and computing contexts, including:

• Cryptographic hardware requiring resistance to clock-based side-channel attacks
• Ultra-low-power sensor nodes operating at variable supply voltages
• Radiation-hardened processors for space applications
• Interface circuits bridging multiple clock domains within a chip
• High-performance arithmetic datapaths where latency depends on input operand values