Conferences related to Superconducting logic circuits

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2020 IEEE/PES Transmission and Distribution Conference and Exposition (T&D)

Bi-Annual IEEE PES T&D conference. Largest T&D conference in North America.


2018 9th International Particle Accelerator Conference (IPAC)

Topics cover a complete survey of the field of charged particle accelerator science and technology and infrastructure.


2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)

Nanotechnology


2018 IEEE International Test Conference (ITC)

International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification and validation, test (DFT, ATPG, and BIST), diagnosis, failure analysis and back to process, yield, reliability and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.


2018 International Conference on Power, Signals, Control and Computation (EPSCICON)

The scope of the conference is essentially inter-disciplinary though we have identified four broad areas- Power & Energy systems, Control & vibration analysis, signals& circuits and computation. The purpose of the conference is to bring together specialists, researchers and teachers in all areas of electrical and other associated branches of engineering for an effective exchange of ideas and discussions on future directions of research and teaching. As a prelude to the Centre for Science and Engineering Computation we are setting up in our institution, a few workshop/ tutorials on various inter-disciplinary topics are also being organized. They shall be related to the conference and delivered by eminent personalities from well recognized Universities, IIT'S and industries. We hope to bring to the scientific community of India research being carried out in different parts of the world through this conference.

  • 2014 International Conference on Power Signals Control and Computations (EPSCICON)

    The scope of the conference is essentially inter-disciplinary though we have identified four broad areas- Power & Energy systems, Control & vibration analysis, signals& circuits and computation.The purpose of the conference is to bring together specialists, researchers and teachers in all areas of electrical and other associated branches of engineering for an effective exchange of ideas and discussions on future directions of research and teaching. As a prelude to the Centre for Science and Engineering Computation we are setting up in our institution, a few workshop/ tutorials on various inter-disciplinary topics are also being organized. They shall be related to the conference and delivered by eminent personalities from well recognized Universities, IIT

  • 2012 International Conference on Power, Signals, Controls and Computation (EPSCICON)

    The major themes of the conference include Power and Energy Systems and Power Electronics, Control Systems including Power and Vibration Control, Signal and Image Processing, Circuit Theory, Networks and Communication, System Identification, Mathematical Systems Theory, Mathematical, Computational and optimization Methods in Engineering, Engineering Education,Computer-Aided Control Systems Design and Analysis, and Software for Systems Design and Analysis.Besides plenary talks, there will be sessions of contributed talks and semi-plenary talks to be given by young and talented scientists and tutorials or workshops.


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Periodicals related to Superconducting logic circuits

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computing in Science & Engineering

Physics, medicine, astronomy—these and other hard sciences share a common need for efficient algorithms, system software, and computer architecture to address large computational problems. And yet, useful advances in computational techniques that could benefit many researchers are rarely shared. To meet that need, Computing in Science & Engineering (CiSE) presents scientific and computational contributions in a clear and accessible format. ...


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


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Most published Xplore authors for Superconducting logic circuits

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Xplore Articles related to Superconducting logic circuits

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Complementary Josephson junction devices and circuits: a possible new approach to superconducting electronics

IEEE Transactions on Applied Superconductivity, 1998

We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the ...


Signaling with Conserved Quantities: Two Realizations in CMOS and Superconducting Flux Quantum Logic

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007

A simple scheme for single rail asynchronous data transmission and signaling relying on the management and transfer of conserved quantities is presented. The conserved quantity is dependent on the kind of logic family used: mass for fluidic logic, charge for CMOS logic, and flux for superconducting flux quantum logic.


Margins and yield in superconducting circuits with gain

IEEE Transactions on Applied Superconductivity, 1997

We analyze the relationship between current gain and circuit critical current margins in prototype vortex flow transistor (VFT) circuits. We give a brief review of the relationship between process spread, circuit margins, and yield. We note that modest increases in gain could dramatically improve yield. In some of the circuits previously proposed, however, there is a limit to the gain ...


A subnanosecond cycle time chip in Josephson technology

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982

THIS PAPER will describe the design and performance of a subnanosecond cycle time logic chip in Josephson technology. A data processing circuit, implemented in 2.5pm Josephson Current Injection Logic (CIL)1 has been tested at cycle times as small as 665ps The chip power dissipation was about 350pW. The circuit contained OR gates, AND gates, EX-OR gates and latches - equivalent ...


Monte Carlo optimization of superconducting complementary output switching logic circuits

IEEE Transactions on Applied Superconductivity, 1998

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described ...


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Educational Resources on Superconducting logic circuits

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IEEE.tv Videos

Low-energy High-performance Computing based on Superconducting Technology
ASC-2014 SQUIDs 50th Anniversary: 1 of 6 Arnold Silver
The Josephson Effect: Josephson Digital Electronics in the Soviet Union
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
Quantum Computation - ASC-2014 Plenary series - 4 of 13 - Tuesday 2014/8/12
Multi-Level Optimization for Large Fan-In Optical Logic Circuits - Takumi Egawa - ICRC 2018
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
The Prospects for Scalable Quantum Computing with Superconducting Circuits - Applied Superconductivity Conference 2018
Nanophotonic Devices for Quantum Information Processing: Optical Computing - Carsten Schuck at INC 2019
The Josephson Effect: The Original SQUIDs
Quantum Annealing: Current Status and Future Directions - Applied Superconductivity Conference 2018
How to Build a Superconducting Opto-Electronic Neuromorphic Computer - Sonia Buckley - ICRC 2018
Stochastic Single Flux Quantum Neuromorphic Computing using Magnetically Tunable Josephson Junctions - Stephen Russek: 2016 International Conference on Rebooting Computing
Voltage Metrology with Superconductive Electronics
"Reversible/Adiabatic Classical Computation An Overview" (Rebooting Computing)
IMS 2011-100 Years of Superconductivity (1911-2011) - Existing and Emerging RF Applications of Superconductivity
Dynamic Logic Example
Applying Control Theory to the Design of Cancer Therapy
BSIM Spice Model Enables FinFET and UTB IC Design

IEEE-USA E-Books

  • Complementary Josephson junction devices and circuits: a possible new approach to superconducting electronics

    We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the complementary device has zero critical current with no input applied. When the input is high, the complementary device has a finite critical current, while the conventional device has zero critical current. The bias current can be steered between a branch with a complementary device and a branch with a conventional device performing logic (and memory) functions. We can also use a resistor as a load to a complementary device. We call this circuit topology the Resistor Complementary Josephson Junction (RCJJ) family. It is analogous to the semiconductor PMOS/resistor logic family. In this paper, we investigate methods of realizing complementary devices, and we present a preliminary analysis of speed, margins, and power dissipation in simple CJJ and RCJJ inverter circuits.

  • Signaling with Conserved Quantities: Two Realizations in CMOS and Superconducting Flux Quantum Logic

    A simple scheme for single rail asynchronous data transmission and signaling relying on the management and transfer of conserved quantities is presented. The conserved quantity is dependent on the kind of logic family used: mass for fluidic logic, charge for CMOS logic, and flux for superconducting flux quantum logic.

  • Margins and yield in superconducting circuits with gain

    We analyze the relationship between current gain and circuit critical current margins in prototype vortex flow transistor (VFT) circuits. We give a brief review of the relationship between process spread, circuit margins, and yield. We note that modest increases in gain could dramatically improve yield. In some of the circuits previously proposed, however, there is a limit to the gain that can be used if proper operation is to be ensured. We introduce alternative approaches to superconducting digital logic families that overcome this limitation in useful gain.

  • A subnanosecond cycle time chip in Josephson technology

    THIS PAPER will describe the design and performance of a subnanosecond cycle time logic chip in Josephson technology. A data processing circuit, implemented in 2.5pm Josephson Current Injection Logic (CIL)1 has been tested at cycle times as small as 665ps The chip power dissipation was about 350pW. The circuit contained OR gates, AND gates, EX-OR gates and latches - equivalent to 102 logic gates, consisting of 177 devices. The gates were powered by an ac power supply2 which was regulated on chip3. The latch circuits were of a self-resetting type, designed for this application.

  • Monte Carlo optimization of superconducting complementary output switching logic circuits

    The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.

  • RSFQ circuitry realized in a SINIS technology process

    We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor- insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j/sub C/=400 A/cm/sup 2/ and a characteristic voltage of V/sub C/=165 /spl mu/V, the area of the smallest junction is A=24 /spl mu/m/sup 2/. The junctions exhibit nearly hysteresis- free current-voltage characteristics (hysteresis: less than 7%), the intra- wafer parameter spread for j/sub C/ is below /spl plusmn/8%. The margins of the bias current I/sub b/ of the circuits have been experimentally determined and found to be larger than /spl plusmn/24%. At preset, constant values of I/sub b/, the range of a separate bias current I/sub bsw/ fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than /spl plusmn/56%.

  • A single-clock asynchronous input COSL set-reset flip-flop and SFQ to voltage state interface

    Although published research in COSL has stagnated, it remains a useful logic family for interfacing the much faster RSFQ family to hot-logic circuits. COSL has always been plagued by the absence of latches, and previous attempts at implementing such latches were clumsy. A new COSL Set-Reset flip-flop is discussed here, and results shown. This asynchronous input latch, which can also be configured as a T flip-flop, can function on a single-phase clock. It was also adapted to convert SFQ output pulses from RSFQ logic circuits to voltage state levels that can be viewed on standard laboratory oscilloscopes. Due to the asynchronous nature of the inputs, the RSFQ-COSL converter is also more reliable than earlier DRO-to-COSL elements.

  • An elementary logic circuit employing superconducting Josephson tunneling gates

    The design and experimental investigation of a simple logic circuit employing Josephson tunnel junctions as the switching elements is described. The design utilized matched transmission lines as signal carriers. The physical layout was simulated on a computer with a model consisting of 3 Josephson gates and 28 transmission line segments. Results of both quasi-static and high speed testing were found to be in essential agreement with theoretical expectations; only dynamic results are presented here in detail. The experimental circuit had gates with 165 ps risetimes, and in the high speed investigation, was operated with bursts of 700 ps risetime pulses tightly spaced so as to simulate a repetition rate of ∼1 GHz.

  • Next generation Nb superconductor integrated circuit process

    We have developed our next generation Nb integrated circuit process which offers higher performance, particularly for SFQ-type logic, and increased density compared to our present 2000 A/cm/sup 2/ foundry process. The new process is based on our existing Nb foundry process, but has been optimized to utilize more of the sub-micron alignment and exposure capabilities of our optical lithography tools. Minimum linepitch and junction size have been reduced to 2.5 /spl mu/m (from 4 /spl mu/m) and 1.75 /spl mu/m (from 2.5 /spl mu/m), respectively, and J/sub c/ has been increased to 4000 A/cm/sup 2/. These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF/sub 6/ dry etch for metal line definition, and optimization of the photolithography process. The new process offers lower inductance wiring and substantially lower parasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test data for devices fabricated in this process.

  • Optimised asynchronous self-timing for superconducting RSFQ logic circuits

    Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested



Standards related to Superconducting logic circuits

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