Adaptive Bandwidth Pll
81 resources related to Adaptive Bandwidth Pll
- Topics related to Adaptive Bandwidth Pll
- IEEE Organizations related to Adaptive Bandwidth Pll
- Conferences related to Adaptive Bandwidth Pll
- Periodicals related to Adaptive Bandwidth Pll
- Most published Xplore authors for Adaptive Bandwidth Pll
IEEE-ECCE 2019 brings together practicing engineers, researchers, entrepreneurs and other professionals for interactive and multi-disciplinary discussions on the latest advances in energy conversion technologies. The Conference provides a unique platform for promoting your organization.
ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.
ICASSP is the world’s largest and most comprehensive technical conference focused on signal processing and its applications. The conference will feature world-class presentations by internationally renowned speakers, cutting-edge session topics and provide a fantastic opportunity to network with like-minded professionals from around the world.
Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAM
NEWCAS2018 will encompass a wide range of special sessions and keynote talks given by prominent expertscovering key areas of research in microsystems in order to provide all attendees a unique forum for the exchange of ideas and results. The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared by researchers in this field.
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)
Theory and applications of industrial electronics and control instrumentation science and engineering, including microprocessor control systems, high-power controls, process control, programmable controllers, numerical and program control systems, flow meters, and identification systems.
The fundamental nature of the communication process; storage, transmission and utilization of information; coding and decoding of digital and analog communication transmissions; study of random interference and information-bearing signals; and the development of information-theoretic techniques in diverse areas, including data communication and recording systems, communication networks, cryptography, detection systems, pattern recognition, learning, and automata.
Science and technology related to the basic physics and engineering of magnetism, magnetic materials, applied magnetics, magnetic devices, and magnetic data storage. The Transactions publishes scholarly articles of archival value as well as tutorial expositions and critical reviews of classical subjects and topics of current interest.
2011 4th IEEE International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2011
Adaptive bandwidth PLL design based on fuzzy logic control is presented for the problem of tracking poor stability and low accuracy when a certain type of radar tracking dynamic spacecraft. This method is mainly through fuzzy logic controller, adaptive level is determined by control rule of input respectively, and the outputs of rules are weighted combined to control the coefficient ...
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008
This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL. The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly. The maximum calibration time is less than five comparison periods. With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole ...
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013
DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator . In general, the sensitivity ...
2015 International Symposium on Signals, Circuits and Systems (ISSCS), 2015
This paper describes a new method for the design of wide range adaptive bandwidth PLLs. This method is implemented in two steps. In the first step named as coarse calibration, CCO (current controlled oscillator) center current is found using a digital frequency comparator. Voltage-to-current converters driving the CCO have a constant input voltage range. Additionally, their output current range is ...
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003
A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18/spl mu/m technology. The prototype 8-context, 8/spl times/8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm/sup 2/. Based on 2/spl times/2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, ...
IMS 2014: Wideband mmWave Channels: Implications for Design and Implementation of Adaptive Beam Antennas
A Fully Integrated 75-83GHz FMCW Synthesizer for Automotive Radar Applications with -97dBc/Hz Phase Noise at 1MHz Offset and 100GHz/mSec Maximal Chirp Rate: RFIC Industry Showcase 2017
Neuromorphic Adaptive Edge-preserving Denoising Filter: IEEE Rebooting Computing 2017
An Analysis of Phase Noise Requirements for Ultra-Low-Power FSK Radios: RFIC Interactive Forum 2017
A Low Power High Performance PLL with Temperature Compensated VCO in 65nm CMOS: RFIC Interactive Forum
A 40GHz PLL with -92.5dBc/Hz In-Band Phase Noise and 104fs-RMS-Jitter: RFIC Interactive Forum 2017
What's New in Digital Predistortion
A Wideband Single-PLL RF Receiver for Simultaneous Multi-Band and Multi-Channel Digital Car Radio Reception: RFIC Industry Showcase
Applications of Adaptive Critic Design 1
Applications of Adaptive Critic Design 2
Robotics History: Narratives and Networks Oral Histories: Minoru Asada
Compact 75GHz PA with 26.3% PAE & 24GHz Bandwidth - Stephen Callender - RFIC Showcase 2018
Transportation Electrification: Connected Vehicle Environment
2013 IEEE Dennis J. Picard Medal
Overcoming the Static Learning Bottleneck - the Need for Adaptive Neural Learning - Craig Vineyard: 2016 International Conference on Rebooting Computing
IMS 2015: Edward Tong - John Tucker Special Tribute - Ultra-wide IF Bandwidth - The Next Frontier for SIS Receivers
A 30-MHz-to-3-GHz CMOS Array Receiver with Frequency and Spatial Interference Filtering for Adaptive Antenna Systems: RFIC Industry Showcase
A Fully-Integrated SOI CMOS Complex-Impedance Detector for Matching Network Tuning in LTE Power Amplifier: RFIC Interactive Forum
IEEE Jun-Ichi Nishizawa Medal - Joe C. Campbell - 2018 IEEE Honors Ceremony
Adaptive bandwidth PLL design based on fuzzy logic control is presented for the problem of tracking poor stability and low accuracy when a certain type of radar tracking dynamic spacecraft. This method is mainly through fuzzy logic controller, adaptive level is determined by control rule of input respectively, and the outputs of rules are weighted combined to control the coefficient of loop filter, thus adjusting automatically the loop bandwidth, and enhancing the tracking stability of radar equipment and improving ranging accuracy. The simulation results show that the fuzzy logic control adaptive bandwidth PLL has higher tracking stability and accuracy.
This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL. The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly. The maximum calibration time is less than five comparison periods. With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole working range. The proposed circuit has been implemented in 0.18 um CMOS logic process. Results show that the calibration time is less than 1.2¿s, and the total locking time is less than 3¿s. The PLL has good jitter performance within its operating range from 860 MHz to 2.1GHz.
DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator . In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance . Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface . However, the complexity of the transmitter and the C<sub>IO</sub>, capacitance of I/O, increase due to additional equalizers and pre- and de-emphasis drivers. For a compact transmitter, a low-overhead boosted transmitter is developed . This paper presents an adaptive-bandwidth PLL in response to the supply and channel noises, a fast pre-charged data sampler without an additional decision- feedback equalizer (DFE), a crosstalk-induced-jitter-reduction technique and a compact transmitter with pre- and de-emphasis.
This paper describes a new method for the design of wide range adaptive bandwidth PLLs. This method is implemented in two steps. In the first step named as coarse calibration, CCO (current controlled oscillator) center current is found using a digital frequency comparator. Voltage-to-current converters driving the CCO have a constant input voltage range. Additionally, their output current range is proportional to the CCO center current, so VCO gain tracks the center frequency. Charge pump current is also determined based on the update frequency in this step. In the second step named as fine tuning, CCO locks to the target frequency with a phase frequency detector (PFD) around the center current found in the first step. VCO gain tracking and finding the charge pump current based on the update frequency make the natural frequency proportional to the update frequency. Sample-reset loop filter provides a tracking mechanism between the update rate and the stabilizing zero. Furthermore, both the natural frequency and the stabilizing zero are made dependent on the ratio of circuit elements and bandgap reference voltages. This makes the loop dynamics less sensitive to process and temperature variations and virtually independent of output frequency and multiplication factor. The PLL has 500-2500MHz output frequency range and 1 to 50MHz update frequency range. The design was simulated in 0.18μm CMOS technology to verify the proposed method.
A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18/spl mu/m technology. The prototype 8-context, 8/spl times/8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm/sup 2/. Based on 2/spl times/2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, with independent clocks at both ends.
A transistor-based background on-chip self-calibration technique is proposed to obtain PVT-independent circuit parameters. With little implementation complexity, the proposed direct I-V calibration of performance determining transistors efficiently achieves stable operation of precision circuits. As an example application to a design of a PLL, the calibration scheme adjusts critical parameters such as VCO gain and charge-pump current to achieve adaptive bandwidth characteristics. The PLL, implemented in a 0.18 mum CMOS, shows a wide lock-range of 10 MHz-1 GHz with the rms jitter of 5.7 ps at 1 GHz.
Phase-locked loops (PLL) are widely used for clock recovery in digital communication receivers because they generate a necessary clock signal with relatively low hardware cost. The PLLs used in receivers are usually required to generate a low-jitter clock, but at the same time, to achieve fast frequency and phase lock. Conventional analog PLLs can generate a low-jitter clock signal with a narrow loop bandwidth, at the expense of lengthened locking time. As an alternative, a digital PLL or a hybrid analog/digital PLL can achieve a 50-cycle lock with a 125 ps jitter from an unknown frequency. But, its inherent complexity causes problems such as a large die, low speed, and high power consumption. A sophisticated loop bandwidth control algorithm is applied such as a gear-shifting or a lock-detection algorithm to the conventional analog PLLs. Here, the PLLs dynamically control the loop bandwidth by changing the charge-pump current in real time according to a well-designed current control sequence stored in its memory. However, in many applications such as high-speed HDDs and DVDs under the influence of phase fluctuation, instant frequency shift, and varying jitter, the stored fixed sequence in its memory is not adequate. This gear-shifting PLL achieves fast locking with low jitter in a time-varying channel.
In phase-locked loop (PLL), the loop parameters such as loop bandwidth, phase margin and damping factor must be adjusted to minimize jitter and to guarantee stability. According to the restrictions of the PLL, this paper employs formula derives to find the relationship between the loop parameters. Therefore, the PLL uses time-to-digital converter (TDC) and programmable current mirror (PCM) to adjust loop parameters that can apply to provide the wide operating frequency range and low-jitter performance. The chip is fabricated in a 0.18-μm standard CMOS process with a 1.8 V power supply voltage and consumes 8 mW at 400 MHz operation frequency. The measured output operating frequency range is 100 MHz-1 GHz, the input reference frequency range is 5 MHz-100 MHz, and the jitter is less than 3.3 % of the output period.
A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.
A phase-locked loop (PLL) and delay-locked loop (DLL) design with adaptively adjusting bandwidth enables optimal performance over a wide frequency range and across process, voltage, and temperature variations. A design methodology of such adaptive-bandwidth PLLs and DLLs is described. To assess the impact of each circuit parameter directly, we derive a discrete-time, open-loop dynamic model of the PLL/DLL that characterizes the change in output variables in response to the sampled error and we express the adaptive-bandwidth criteria in terms of the open-loop gains, instead of the traditional closed-loop parameters, /spl omega//sub n/ and /spl zeta/. Applying these criteria, we derive scaling equations for the charge-pump current and filter resistance that achieve adaptive bandwidth in charge-pump PLL/DLLs. We show that previously published adaptive-bandwidth PLL/DLLs, a self-biased PLL/DLL and a regulated-supply PLL/DLL, rely on the small-signal conductance tracking the large-signal conductance of the voltage-controlled oscillator/voltage- controlled delay-line and, thus, sustain constant /spl omega//sub n///spl omega//sub ref/ and /spl zeta/ only if the voltage swing is sufficiently higher than the device threshold voltage V/sub TH/. The paper also presents procedures to estimate the open-loop parameters from an open-loop impulse response of the PLL/DLL.
No standards are currently tagged "Adaptive Bandwidth Pll"