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The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE
2020 IEEE 18th International Conference on Industrial Informatics (INDIN)
INDIN focuses on recent developments, deployments, technology trends, and research results in Industrial Informatics-related fields from both industry and academia
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.
IEEE Global Communications Conference (GLOBECOM) is one of the IEEE Communications Society’s two flagship conferences dedicated to driving innovation in nearly every aspect of communications. Each year, more than 2,900 scientific researchers and their management submit proposals for program sessions to be held at the annual conference. After extensive peer review, the best of the proposals are selected for the conference program, which includes technical papers, tutorials, workshops and industry sessions designed specifically to advance technologies, systems and infrastructure that are continuing to reshape the world and provide all users with access to an unprecedented spectrum of high-speed, seamless and cost-effective global telecommunications services.
All fields of satellite, airborne and ground remote sensing.
Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...
Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.
Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing
IEEE Computer Graphics and Applications (CG&A) bridges the theory and practice of computer graphics. From specific algorithms to full system implementations, CG&A offers a strong combination of peer-reviewed feature articles and refereed departments, including news and product announcements. Special Applications sidebars relate research stories to commercial development. Cover stories focus on creative applications of the technology by an artist or ...
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Electro International, 1991, 1991
Cache memories are moving into the forefront of popularity. Most microprocessor system designers can now expect to be called upon to design or implement a cache at some time in their carreers. It is somewhat difficult deciding where to start when first confronted with the task of designing a cache from scratch. This paper will focus on techniques which can ...
Tsinghua Science and Technology, 2007
The growing size of the multiprocessor systems increases their vulnerability to component failures. It is crucial to local and to replace the fault processors to maintain system's high reliability. The fault diagnosis is the process of identifying faulty processors in a system through testing. This paper establishes the diagnosabilities of the incomplete star graph Sn(n> 4) with missing links under ...
 Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium, 1991
The authors previously (1989) presented algorithms in which if at least two processors perform tests on any given processor, the probability of correct diagnosis approaches one as N to infinity if the number of tests performed by each tester on each processor under test is O(log N). The algorithm was based on a comparison approach to probabilistic system-level fault diagnosis ...
IEEE Transactions on Nuclear Science, 1985
MLLE is a multiprocessor system for data acquisition and processing in nuclear physics applications. A large memory allows accumulation of megachannel histograms  . The system is built from VMEbus modules and interfaces CAMAC. MLLE is connected to a host computer under UNIX, where graphic representation and mathematical analysis can be done. On the MLLE a UNIX-like environment is established. ...
2009 International Conference on Computational Intelligence and Software Engineering, 2009
With the emergence of multicore processors, parallel software is beginning to be used in the domain of application development in addition to high performance computing. In this work three software design patterns are chosen from each pattern category as subjects, representing reusable elements of object oriented software design. Behavior of these patterns in a shared memory parallel environment is investigated ...
Open Systems Architecture for RF and Microwave Technologies: MicroApps 2015 - Mercury Systems
IMS 2011 Microapps - Calibration and Accuracy in Millimeter Systems
Impact on Society: Systems Engineer to Systems Entrepreneur for Global Change - Erna Grasz at the 2017 IEEE VIC Summit
Innovative Mechanical Systems to Address Current Robotics Challenges
Harold "Bud" Lawson - IEEE Simon Ramo Medal, 2019 IEEE Honors Ceremony
A Thermodynamic Treatment of Intelligent Systems - IEEE Rebooting Computing 2017
Inside Kiva Systems - Warehouse Robots at Work
ITEC 2014: Urban Mass Transit Systems: Current Status and Future Trends
Rebooting Computing: Trust and Security in Future Computing Systems
IROS TV 2019- Maryland Robotics Center, Institute for Systems Research, University of Maryland
Augmented Reality in Operating Rooms
EMBC 2011-Program-Systems in Synthetic Biology (Part I)-Pamela A. Silver
Wireless Charging Systems for EVs
EMBC 2011-Workshop- Biological Micro Electro Mechanical Systems (BioMEMS): Fundamentals and Applications-Utkan Demirci
The Future of Home & Factory Automation Systems: Mouser's Innovation Spotlight with Grant Imahara
Continuously Learning Neuromorphic Systems with High Biological Realism: IEEE Rebooting Computing 2017
Research, Development and Field Test of Robotic Observation Systems for Active Volcanic Areas in Japan
IEEE Green Energy and Systems Conference 2015
Intelligent Transportation Systems Society: Changing how the world moves
Cache memories are moving into the forefront of popularity. Most microprocessor system designers can now expect to be called upon to design or implement a cache at some time in their carreers. It is somewhat difficult deciding where to start when first confronted with the task of designing a cache from scratch. This paper will focus on techniques which can be used in microprocessor cache designs to improve system throughput. Examples are shown using Intel's i486 processor, and the P3000 RISC processor.
The growing size of the multiprocessor systems increases their vulnerability to component failures. It is crucial to local and to replace the fault processors to maintain system's high reliability. The fault diagnosis is the process of identifying faulty processors in a system through testing. This paper establishes the diagnosabilities of the incomplete star graph Sn(n> 4) with missing links under the PMC model and its variant, the BGM model, and shows that the diagnosabilities of incomplete star graph Snunder these two diagnostic models can be determined by the minimum degree of its topology structure. This method can also be applied to the other existing multiprocessor systems.
The authors previously (1989) presented algorithms in which if at least two processors perform tests on any given processor, the probability of correct diagnosis approaches one as N to infinity if the number of tests performed by each tester on each processor under test is O(log N). The algorithm was based on a comparison approach to probabilistic system-level fault diagnosis in which processors may perform multiple tests on other processors. Here they present a new hierarchical testing algorithm for this model and show that asymptotically efficient testing can be done when the product of number of testers*number of tests each performs on a processor grows as O(log N) as N to infinity . The method thus preserves the topological flexibility of the previous method, while allowing the number of tests each tester must perform to be tailored to the requirements of the topology.<<ETX>>
MLLE is a multiprocessor system for data acquisition and processing in nuclear physics applications. A large memory allows accumulation of megachannel histograms  . The system is built from VMEbus modules and interfaces CAMAC. MLLE is connected to a host computer under UNIX, where graphic representation and mathematical analysis can be done. On the MLLE a UNIX-like environment is established. The operating system DAMOS of MLLE allows dataflow controlled processing using about ten microprocessors operating in a non-hierarchica] mode.
With the emergence of multicore processors, parallel software is beginning to be used in the domain of application development in addition to high performance computing. In this work three software design patterns are chosen from each pattern category as subjects, representing reusable elements of object oriented software design. Behavior of these patterns in a shared memory parallel environment is investigated regarding different aspects of parallelization including parallelizability, scalability and workload distribution.
This paper investigates the effectiveness of parallel computing in the calculation of the bispectrum. The bispectrum is estimated by using two different methods namely the direct and the indirect. The direct method employs 1-D FFT algorithms and the indirect method employs the 2-D FFT algorithm to estimate the bispectrum. Both methods have been implemented using 2 different parallel programming techniques: semi-automatic and fully automatic using the Power C Analyzer (PCA). The Silicon Graphics Power Challenge Multiprocessor System (with 12 CPUs) is used to run the parallel codes. Near-linear speedup was observed by employing both techniques. Overall, the maximum speedup of 10.84 at N=12 can be achieved for the direct method and of 8.7 at N=10 for the indirect method using the semi-automatic parallel technique. For the PCA fully parallel technique, the maximum measured speedup for the direct and indirect methods are 10.07 at N=11 and 7.67 at N=12 respectively.
Summary form only given. Inherent limitations on the computational power of sequential uniprocessor systems have led to the development of parallel multiprocessor systems. The two major issues in the formulation and design of parallel multiprocessor systems are algorithm design and architecture design. The parallel multiprocessor systems should be so designed so as to facilitate the design and implementation of the efficient parallel algorithms that exploit optimally the capabilities of the system. From an architectural point of view, the system should have low hardware complexity, be capable of being built of components that can be easily replicated, should exhibit desirable cost-performance characteristics, be cost effective and exhibit good scalability in terms of hardware complexity and cost with increasing problem size. In distributed memory multiprocessor systems, the processing elements can be considered to be nodes that are connected together via an interconnection network. In order to facilitate algorithm and architecture design, we require that the interconnection network have a low diameter, the system be symmetric and each node in the system have low degree of connectivity. Further, it is also desirable that the system configuration and behavior be amenable to a suitable and tractable mathematical description. The requirement of network symmetry ensures that each node in the network is identical to any other, thereby greatly reducing the architecture and algorithm design effort. For most symmetric network topologies, however, the requirements of low degree of connectivity for each node and low network diameter are often conflicting. Low network diameter often entails that each node in the network have a high degree of connectivity resulting in a drastic increase in the number of inter-processor connection links. A low degree of connectivity on the other hand, results in a high network diameter which in turn results in high inter-processor communication overhead and reduced efficiency of parallelism. Reconfigurable networks attempt to address this tradeoff. In a reconfigurable network each node has a fixed degree of connectivity irrespective of the network size. The network diameter is restricted by allowing the network to reconfigure itself into different configurations. Broadly speaking, a reconfigurable system needs to satisfy the following criteria in order to be considered practically viable: (a) In each configuration the nodes in the network should have a fixed degree of connectivity irrespective of network size, (b) The network diameter should be kept low via the reconfiguration mechanism and (c) The hardware for the reconfiguration mechanism (i.e., switch) should be of reasonable complexity. In this presentation, we discuss our design of a reconfigurable network topology that is targeted at medical applications. We present some results and discuss the future roadmap of this project.
Diagnosis is an essential subject for the reliability of multiprocessor systems. Under the PMC diagnosis model, Dahbura and Masson proposed a polynomial-time algorithm with time complexity O(N<sup>2.5</sup>) to identify all the faulty processors in a system with N processors. In this paper, we present a novel method to diagnose a conditionally faulty system by applying the concept behind the local diagnosis, introduced by Somani and Agarwal, and formalized by Hsu and Tan. The goal of local diagnosis is to identify the fault status of any single processor correctly. Under the PMC diagnosis model, we give a sufficient condition to estimate the local diagnosability of a given processor. Furthermore, we propose a helpful structure, called the augmenting star, to efficiently determine the fault status of each processor. For an N-processor system in which every processor has an O(log N) degree, the time complexity of our algorithm to diagnose any given processor is O((log N)<sup>2</sup>), provided that each processor can construct an augmenting star structure of full order in time O((log N)<sup>2</sup>) and the time for a processor to test another one is constant. Therefore, the time totals to O(N(log N)<sup>2</sup>) for diagnosing the whole system.