IEEE Transactions on Semiconductor Manufacturing

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The IEEE Transactions on Semiconductor Manufacturing (SM) is a quarterly journal published by the IEEE Computer Society. (Wikipedia.org)




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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


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The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


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The IEEE Transactions on Automation Sciences and Engineering (T-ASE) publishes fundamental papers on Automation, emphasizing scientific results that advance efficiency, quality, productivity, and reliability. T-ASE encourages interdisciplinary approaches from computer science, control systems, electrical engineering, mathematics, mechanical engineering, operations research, and other fields. We welcome results relevant to industries such as agriculture, biotechnology, healthcare, home automation, maintenance, manufacturing, pharmaceuticals, retail, ...


Biomedical Circuits and Systems, IEEE Transactions on

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Guest Editorial Special Section on the Advanced Semiconductor Manufacturing Conference

IEEE Transactions on Semiconductor Manufacturing, 2011

This special section of the IEEE TRANSACTIONS ON Semiconductor Manufacturing (TSM) provides a wider dissemination of selected material presented at the 2010 ASMC to the semiconductor manufacturing community. One paper discusses the structural and electrical characterization of ALD-deposited high-k films. Defects are studied in three papers from different perspectives; one focuses on a library of different types of defects, the ...


Enhancement of CMOS performance by process-induced stress

IEEE Transactions on Semiconductor Manufacturing, 2005

A detailed analysis of the process-induced stress during a standard CMOS manufacturing is presented. Dependence of transistor performance on layout is attributed to the combination of stress induced by shallow trench isolation and source/drain (S/D) silicide. Based on the layout sensitivity, the effect of an individual stress component on NMOS and PMOS is identified. The optimization of transistor layout is ...


Biofilter technology: an innovative and cost-effective system to remove VOC

IEEE Transactions on Semiconductor Manufacturing, 2004

Biofilter technology is a cost-effective technique with an excellent efficiency for volatile organic compound (VOC) treatment. It is an attractive alternative to conventional air pollution abatement technologies. In this project, a combination of a Biosrubber and a Biofilter (called Biofilter System) was tested with VOC-laden exhaust air from a semiconductor fab. This Biofilter System meets all requirements of German and ...


Advanced gate etching for accurate CD control for 130-nm node ASIC manufacturing

IEEE Transactions on Semiconductor Manufacturing, 2004

This paper presents a methodology for gate trim etching to obtain accurate critical dimension (CD) control for 130-nm node ASIC manufacturing. In order to reduce mask-to-mask CD variation in gate trim etching, correlation between mask layout and amount of gate trim is investigated. It is found that trim rate strongly depends on gate peripheral length. A novel feed-forward technology to ...


Statistical methods for visual defect metrology

IEEE Transactions on Semiconductor Manufacturing, 1998

Automated systems are used to inspect unpatterned and product wafers for particulates and other defects. Wafer defect count and defect density statistics are used as process control parameters, but are known to be deceptive in the presence of defect clustering. An improvement path using novel visual defect metrology statistical analyses is proposed. Quadrat analysis, nested analysis of variance, and principal ...


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IEEE-USA E-Books

  • Guest Editorial Special Section on the Advanced Semiconductor Manufacturing Conference

    This special section of the IEEE TRANSACTIONS ON Semiconductor Manufacturing (TSM) provides a wider dissemination of selected material presented at the 2010 ASMC to the semiconductor manufacturing community. One paper discusses the structural and electrical characterization of ALD-deposited high-k films. Defects are studied in three papers from different perspectives; one focuses on a library of different types of defects, the second studies failure rate estimation of each process layer using critical area analysis and failing bit results, while the third reduces the electrostatically adhered particles on wafer backside by using ionizers. Lithography applications are discussed in one paper, where bright field defect inspection is employed for process window centering at the 22 nm node, and in another where topcoat-less resists are evaluated for high volume immersion lithography. One paper details the neural networks for advanced process control while another investigates yield improvement using a scalable parametric measurement macro. Finally, rule induction for identifying multilayer tool commonalities is evaluated.

  • Enhancement of CMOS performance by process-induced stress

    A detailed analysis of the process-induced stress during a standard CMOS manufacturing is presented. Dependence of transistor performance on layout is attributed to the combination of stress induced by shallow trench isolation and source/drain (S/D) silicide. Based on the layout sensitivity, the effect of an individual stress component on NMOS and PMOS is identified. The optimization of transistor layout is proposed to improve the CMOS performance.

  • Biofilter technology: an innovative and cost-effective system to remove VOC

    Biofilter technology is a cost-effective technique with an excellent efficiency for volatile organic compound (VOC) treatment. It is an attractive alternative to conventional air pollution abatement technologies. In this project, a combination of a Biosrubber and a Biofilter (called Biofilter System) was tested with VOC-laden exhaust air from a semiconductor fab. This Biofilter System meets all requirements of German and European law and protects the environment. The results of this project demonstrate that it is possible to establish this innovative and emerging technology in the semiconductor industry.

  • Advanced gate etching for accurate CD control for 130-nm node ASIC manufacturing

    This paper presents a methodology for gate trim etching to obtain accurate critical dimension (CD) control for 130-nm node ASIC manufacturing. In order to reduce mask-to-mask CD variation in gate trim etching, correlation between mask layout and amount of gate trim is investigated. It is found that trim rate strongly depends on gate peripheral length. A novel feed-forward technology to reduce both wafer-to-wafer variation and mask-to-mask variation is developed with the knowledge of peripheral length effect. This technology can also reduce CD variation within die and the CD bias between dense and isolated lines is compensated by optical proximity correction rules. This novel feed-forward technology is one solution for improving every gate CD variation: within die, within wafer, wafer-to-wafer, and mask-to-mask.

  • Statistical methods for visual defect metrology

    Automated systems are used to inspect unpatterned and product wafers for particulates and other defects. Wafer defect count and defect density statistics are used as process control parameters, but are known to be deceptive in the presence of defect clustering. An improvement path using novel visual defect metrology statistical analyses is proposed. Quadrat analysis, nested analysis of variance, and principal component analysis use data available currently. Spatial point pattern statistics and spatial pattern recognition require special algorithms. Future process control systems made possible by these statistical analyses are discussed.

  • All Regimes Parasitic Capacitances Extraction Using a Multi-Channel CBCM Technique

    In this paper, we propose a multi-channel charge-based capacitance measurement (MCCBCM) technique for parasitic capacitances extraction of MOSFETs. The proposed technique is developed from a leakage- and parasitic-insensitive charge-based capacitance measurement technique, which is applied to measure gate-to-channel capacitance in certain regimes. Using the MCCBCM technique, we can measure all of the parasitic capacitance components of an MOSFET which are related to its terminals, such as the gate-to drain capacitance (C<sub>GD</sub>), gate-to-source capacitance (C<sub>GS</sub>), gate-to-bulk capacitance (C<sub>GB</sub>), and so on. We designed a complex control methodology for the MCCBCM circuit. Specific control methods are provided for different parasitic capacitance components when MOSFETs work in different regimes. We can measure capacitances of subfemto-farad level in all regimes, including the accumulation, depletion, and inversion regimes.

  • Defect detection algorithm for wafer inspection based on laser scanning

    A defect detection algorithm for wafer inspection based on laser scanning is presented. Microscopic anomalies, contaminants, and process induced pattern defects result in a two-dimensional (2-D) laser scattering signature, which closely resembles the coherent point-spread-function of the scanning laser beam. This point-spread-function is a 2-D Gaussian in the majority of cases and can be characterized by four parameters. The algorithm fits Gaussian surfaces to sampled data points. Events are accepted or rejected on the basis of how similar the Gaussian parameters are to that of the point-spread- function, known a priori. It is shown that the algorithm achieves a 95% capture for submicron particles and pattern defects on typical logic and array wafer regions. Results demonstrating the algorithm's performance relative to mechanical and electronic noise and to signal resolution are presented.

  • Improved EEPROM tunnel- and gate-oxide quality by integration of a low-temperature pre-tunnel-oxide RCA SC-1 clean

    The effects of integration of a low-temperature RCA standard clean-1 (SC1) on the tunnel- and gate-oxide charge-to-breakdown (Q/sub BD/) and voltage ramped dielectric breakdown (VRDB) distribution in a 0.7 /spl mu/m CMOS EEPROM process technology were studied. A low-temperature (<65/spl deg/C) SC1 used to clean the wafer surface prior to tunnel oxidation resulted in a significantly higher tunnel-oxide Q/sub BD/, as well as improved gate-oxide Q/sub BD/ and mode-B failure rates compared to that for a traditional high temperature (>80/spl deg/C) SC1. The reduced silicon diode etchrate of the low-temperature SC1 allowed for additional gate-oxide annealing during the gate oxidation cycle, while keeping the overall thermal budget (Dt)/sup 1/2/ for the technology equivalent to that with the higher temperature SC1. This resulted in improved gate-oxide VRDB distributions and QED values on large capacitor structures. The tunnel-oxide QBD improvement was most likely due to reduced surface roughness in the tunnel-oxide window regions with the lower temperature SC1. The process including the low-temperature SC1 was also proven to provide equivalent yield to the process with the high temperature SC1 on a 0.7 /spl mu/m, 7 nS 128 macrocell EEPROM programmable logic device.

  • High yielding self-aligned contact process for a 0.150-/spl mu/m DRAM technology

    This paper describes improvements in the self-aligned contact process for 0.150 /spl mu/m and 0.175 /spl mu/m technology generations. Using a dynamic random access memory cell layout, we show that self-aligned contacts can be formed at 0.175 /spl mu/m ground rules and beyond by using a C/sub 4/F/sub 8/-CH/sub 2/F/sub 2/ chemistry. With the improved etch selectivity, gate cap nitride thickness can be reduced, resulting in a smaller aspect ratio for the gate etch, borophosphosilicate glass fill, and contact etch. With a rectangular contact, the area can be increased and the process windows for lithography and etch are improved. The process window for lithography increases by up to 40%, the aspect ratio for the etch and the contact fill is less, and the sensitivity to misalignment is reduced. The combination of rectangular contacts and C/sub 4/F/sub 8/-CH/sub 2/F/sub 2/ chemistry greatly enhances the product yield.

  • Equipment Throughput Optimization by Means of Speed Loss Analysis

    Consistent with the semiconductor industry's focus on continuous improvement, increased throughput, and shorter cycle times, this paper describes a methodology for the qualification and quantification of speed loss at a toolset level. The identification and quantification of the speed loss categories, along with implementation of specific actions targeted at these losses, has enabled our fab to have a direct impact on overall capacity and throughput performance of our toolsets.



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