IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, often abbreviated IEEE TCAD or IEEE Transactions on CAD, is a technical journal devoted to the design, analysis, and use of computer programs that aid in the design of integrated circuits and systems. (Wikipedia.org)




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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Fuzzy Systems, IEEE Transactions on

Theory and application of fuzzy systems with emphasis on engineering systems and scientific applications. (6) (IEEE Guide for Authors) Representative applications areas include:fuzzy estimation, prediction and control; approximate reasoning; intelligent systems design; machine learning; image processing and machine vision;pattern recognition, fuzzy neurocomputing; electronic and photonic implementation; medical computing applications; robotics and motion control; constraint propagation and optimization; civil, chemical and ...


Learning Technologies, IEEE Transactions on

The IEEE Transactions on Learning Technologies publishes archival research papers and critical survey papers on technology advances in online learning systems; intelligent tutors; educational software applications and games; simulation systems for education and training; collaborative learning tools, devices and interfaces for learning; interactive techniques for learning; tools for formative and summative assessment; ontologies for learning systems; standards and web services ...


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Guest Editorial

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008

The eight papers in this special section are extended papers that were presented at the International Symposium on Physical Design (ISPD), held in Portland, Oregon, om April 2008.


Filling algorithms and analyses for layout density control

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999

In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into ...


Power supply transient signal analysis for defect-oriented test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003

Transient signal analysis (TSA) is a testing method that is based on the analysis of a set of V/sub DD/ transient waveforms measured simultaneously at each supply port. Defect detection is performed by applying linear regression analysis to the time or frequency domain representations of these signals. Chip-wide process variation effects introduce signal variations that are correlated across the individual ...


Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997

In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level ...


Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985

The method of extracting MOSFET model parameters using optimization offers significant advantages over classical methods of extracting model parameters sequentially. Previous work in this field has concentrated on speed of convergence rather than general applicability. Gradient following methods have been applied to this problem but difficulties arise because of parameter redundancy, singularities in the objective function, and the necessity of ...


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IEEE-USA E-Books

  • Guest Editorial

    The eight papers in this special section are extended papers that were presented at the International Symposium on Physical Design (ISPD), held in Portland, Oregon, om April 2008.

  • Filling algorithms and analyses for layout density control

    In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout. To date, only foundries and special mask data processing tools perform layout post-processing for density control. In the future, better convergence of performance verification flows will depend on such layout manipulations being embedded within the layout synthesis (place-and-route) flow. In this paper, we give the first realistic formulation of the filling problem that arises in layout optimization for manufacturability. Our formulation seeks to add features to a given process layer, such that (1) feature area densities satisfy prescribed upper and lower bounds in all windows of given size and (2) the maximum variation of such densities over all possible window positions in the layout is minimized. We present efficient algorithms for density analysis, notably a multilevel approach that affords user-tunable accuracy. We also develop exact solutions to the problem of fill synthesis, based on a linear programming approach. These include a linear programming (LP) formulation for the fixed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout) and an LP formulation that is automatically generated by our multilevel density analysis. We briefly review criteria for fill pattern synthesis, and the paper then concludes with computational results and directions for future research.

  • Power supply transient signal analysis for defect-oriented test

    Transient signal analysis (TSA) is a testing method that is based on the analysis of a set of V/sub DD/ transient waveforms measured simultaneously at each supply port. Defect detection is performed by applying linear regression analysis to the time or frequency domain representations of these signals. Chip-wide process variation effects introduce signal variations that are correlated across the individual power port measurements. In contrast, defects introduce uncorrelated local variations across these measurements that can be detected as anomalies in the cross-correlation profile derived (using regression analysis) from the power port measurements of defect-free chips. This paper focuses on the application of TSA to the detection of delay faults.

  • Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

    In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.

  • Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method

    The method of extracting MOSFET model parameters using optimization offers significant advantages over classical methods of extracting model parameters sequentially. Previous work in this field has concentrated on speed of convergence rather than general applicability. Gradient following methods have been applied to this problem but difficulties arise because of parameter redundancy, singularities in the objective function, and the necessity of providing very good initial estimates of the model parameters. These factors can seriously hinder the application of the technique. This paper describes the application of the simplex direct search optimization method to this problem. This algorithm, in wide use for general optimization problems, needs no derivative calculation and has proved highly stable for MOS model parameter extraction. Its basis is described and an example of its use given.

  • An algorithm for determining repetitive patterns in very large IC layouts

    This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art IC's which suggest that the diversity of patterns does not significantly increase with increasing chip size.

  • Testability-Driven Random Test-Pattern Generation

    This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability cost function. Using ESPRIT, we have observed orders-of-magnitude reduction in the number of random trials required to obtain a given fault coverage.

  • Statistical Circuit Simulation Modeling of CMOS VLSI

    This paper describes a complete modeling approach for MOS VLSI circuit design which is highly automated and provides statistically relevant parameter files. A description of key model equations, which includes the effects of nonuniformly doped channels, charge sharing bulk-charge terms, and lateral and vertical field mobility reduction terms, will be given. A methodology of parameter extraction for both physical and "fitted" terms will be described. Appropriate distributions of these parameters are then generated and checked for correlations among these parameters. A statistical modeling routine has been developed that then generates device parameter bound files from transformed independent variables. Finally, simulations performed with statistical best-worst case parameter files were compared to data for many transistors from the same lot and process.

  • Improved net merging method for gate matrix layout

    A net-merging method is proposed for gate-matrix layout. The method is based on a density function to calculate the minimum number of tracks necessary for the net assignment. Examples that demonstrate how this method leads to a denser gate matrix layout are included. The pitch of the gate columns is determined by the design rules, in particular, the space required to accommodate a diffused region with an internal contact window between two poly columns. In gate matrix layout, when the space between a pair of gate columns is not sufficient, the spacing between them can be increased locally to two pitches to avoid design rule violation as long as such a local change does not cause column matching problems.<<ETX>>

  • A Procedure for Placement of Standard-Cell VLSI Circuits

    This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.



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