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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.


Electronics Packaging Manufacturing, IEEE Transactions on

Design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally-friendly processing, and computer-integrated manufacturing for the production of electronic assemblies, products, and systems.


Industry Applications, IEEE Transactions on

The development and application of electric systems, apparatus, devices, and controls to the processes and equipment of industry and commerce; the promotion of safe, reliable, and economic installations; the encouragement of energy conservation; the creation of voluntary engineering standards and recommended practices.


Semiconductor Manufacturing, IEEE Transactions on

Addresses innovations of interest to the integrated circuit manufacturing researcher and professional. Includes advanced process control, equipment modeling and control, yield analysis and optimization, defect control, and manufacturability improvement. It also addresses factory modelling and simulation, production planning and scheduling, as well as environmental issues in semiconductor manufacturing.



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Xplore Articles related to IEEE Transactions on Components, Packaging, and Manufacturing Technology Part A

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Production AST with Computers Using the Taguchi Method - Reprinted from Environmental Stress Testing Experiment Using the Taguchi Method, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, Vol. 18, No.1, pp. 39, with permission from the author and the IEEE, 1995.

Accelerated Stress Testing Handbook: Guide for Achieving Quality Products, None

Manufacturing process improvements which increase productivity, decrease test process time, and improve customer satisfaction are highly desirable in today's marketplace. The application of environmental stress screening (ESS), i.e, Production AST, is a method of achieving these improvements. ESS is the application of stresses applied beyond product specification limits in order to find latent product defects. Utilizing ESS achieves increased robustness ...


Study of delaminated plastic packages by high temperature Moire and finite element method

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1997

In the current study, 1200 l/mm gratings are replicated at elevated temperatures onto the cross sections of two delaminated plastic packages: a thin quad flatpack plastic package (TQFPP) and a power small outline plastic package (PSOPP). The specimens are measured at room temperature for thermal deformation induced by cooling process. The finite element models are used to simulate the cooling ...


The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603 and PowerPC 604 RISC microprocessors

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1998

Thermal resistance networks or "compact" models of the PowerPC 603 and PowerPC 604 microprocessors in controlled-collapsed-chip-connection/ceramic-ball-grid- array (C4/CBGA) single-chip package are derived from "detailed" three- dimensional (3-D) conduction models of the parts by both analytical and data fitting techniques. The behavioral correctness of these models is assessed by comparing the die-junction temperatures predicted for the compact model with the detailed ...


Effect of inorganic binders on the properties of thick film copper conductor

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1994

Adhesion strength and solderability of a copper thick film on alumina substrate were studied. Films were prepared with three kinds of inorganic binders, i.e., glass frits, mixture of glass frits and metal oxides, and metal oxides. The effects of inorganic binders on the adhesion and solderability were examined by analyzing physical and chemical behavior of the inorganic binders in the ...


Designing a reliability demonstration test on a lithography expose tool using Bayesian techniques

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1994

Once a wafer fabrication processing tool has demonstrated its potential for meeting process specifications, the focus of tool development broadens to include an assessment of the tool's ability to deliver the specified process repeatedly and reliably over time. Process stability and equipment reliability are assessed in a reliability demonstration test, termed a "marathon" in the SEMATECH Qualification Plan. Statistics plays ...


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IEEE-USA E-Books

  • Production AST with Computers Using the Taguchi Method - Reprinted from Environmental Stress Testing Experiment Using the Taguchi Method, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, Vol. 18, No.1, pp. 39, with permission from the author and the IEEE, 1995.

    Manufacturing process improvements which increase productivity, decrease test process time, and improve customer satisfaction are highly desirable in today's marketplace. The application of environmental stress screening (ESS), i.e, Production AST, is a method of achieving these improvements. ESS is the application of stresses applied beyond product specification limits in order to find latent product defects. Utilizing ESS achieves increased robustness and lowers infant mortality. An experiment was performed to identify the significance or relevancy of the selected stresses for application in the printed wiring assembly (PWA) production process by using a statistically significant controlled method. The_design of experiments_statistical approach (analysis of variance) is applied, combined with the Taguchi two-level, seven-factor design method. This experiment concentrated on three stresses?-?temperature cycling, random vibration, and power cyling?-?and two diagnostic levels?-?a prom-based (programmable memory chip), power-on self test (POST), and a functional diagnostic test suite, contained on disk storage. This was not an optimization experiment. Once the significance to the production process is identified, future optimizing of temperature cycling, power cycling, and vibration screens will be conducted. Also, voltage margining was not included to reduce the complexity of the experiment- treatment factors and interactions. Experimental results and conclusions on the effectiveness of different stress regimens are presented in this chapter. * Introduction * Objectives * Stress Overview * Stress Screen Designs * Experiment Overview * The Taguchi Method * Response Variable Results and Conclusions of the Taguchi Experiment * Intra-Experiment Summary * Taguchi Method Conclusion * Terms * Acknowledgments * References

  • Study of delaminated plastic packages by high temperature Moire and finite element method

    In the current study, 1200 l/mm gratings are replicated at elevated temperatures onto the cross sections of two delaminated plastic packages: a thin quad flatpack plastic package (TQFPP) and a power small outline plastic package (PSOPP). The specimens are measured at room temperature for thermal deformation induced by cooling process. The finite element models are used to simulate the cooling process and the results are compared with the Moire interferometry results. The finite element models with different delaminations between die and die attach are used to simulate the fringe patterns obtained from Moire interferometry. It was found that the delamination size can be estimated by the combination of Moire technique and finite element method. The finite element model, once verified, can then be used in making cost effective decisions in plastic packaging design and processing.

  • The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603 and PowerPC 604 RISC microprocessors

    Thermal resistance networks or "compact" models of the PowerPC 603 and PowerPC 604 microprocessors in controlled-collapsed-chip-connection/ceramic-ball-grid- array (C4/CBGA) single-chip package are derived from "detailed" three- dimensional (3-D) conduction models of the parts by both analytical and data fitting techniques. The behavioral correctness of these models is assessed by comparing the die-junction temperatures predicted for the compact model with the detailed model results for a range of boundary conditions applied at the surfaces of the package. The performance of these models is then verified by comparing the detailed and compact models in an application-specific environment (a wind tunnel) using a computational-fluid dynamics program. The interaction between the package and its environment is also discussed. The work reported here forms part of a long term European research program to create and validate generic thermal models of a range of electronic parts.

  • Effect of inorganic binders on the properties of thick film copper conductor

    Adhesion strength and solderability of a copper thick film on alumina substrate were studied. Films were prepared with three kinds of inorganic binders, i.e., glass frits, mixture of glass frits and metal oxides, and metal oxides. The effects of inorganic binders on the adhesion and solderability were examined by analyzing physical and chemical behavior of the inorganic binders in the copper thick film during firing. The films with an addition of glass frit or mixtures of glass frit and metal oxide did not provide good adhesion and solderability simultaneously. However, the copper thick film containing 10 wt.% bismuth oxide had excellent characteristics, i.e. high adhesion strength, good solderability, and low sheet resistivity.<<ETX>>

  • Designing a reliability demonstration test on a lithography expose tool using Bayesian techniques

    Once a wafer fabrication processing tool has demonstrated its potential for meeting process specifications, the focus of tool development broadens to include an assessment of the tool's ability to deliver the specified process repeatedly and reliably over time. Process stability and equipment reliability are assessed in a reliability demonstration test, termed a "marathon" in the SEMATECH Qualification Plan. Statistics plays a role in the design and interpretation of such testing by supplying the means for 1) specifying test length using the stated reliability goal and prior data on similar tools, and 2) constructing a confidence interval for the estimate of reliability resulting from the test. The design and analysis of a marathon test for a world-class lithography expose tool will be used as an illustration of how statistical methods can be used to advantage in assessing the reliability of a complex system. Most marathon tests conducted at SEMATECH require test times of 500 h or more, resulting in significant test costs. The motivation to reduce test costs without increasing the risk of an incorrect decision is strong. One promising approach to reducing test costs is to incorporate prior equipment performance explicitly in the design of a reliability demonstration test. Previous history and data are usually available from suppliers or users of the equipment to be tested. This paper describes our efforts to reduce test costs for a SEMATECH-sponsored lithography expose tool development project by incorporating past history into the planning of a reliability demonstration test. The statistical method used in this example has been discussed extensively in the statistical literature as a Bayesian application, but it is not widely known to equipment development engineers.<<ETX>>

  • Higher density using diffusion patterned vias and fine-line printing

    This paper discusses design guidelines, process steps, and test results from fabricating two 40-mm MCM-Cs using the latest thick film materials and printing techniques. The two line interface controller (LIC) modules have been designed with two large ASIC's (plus memory) and prototyped using thick film gold conductors with 3-mil line/space and 6-mil via criteria. The second prototype of the LIC module utilized silver conductors at 5-mil line and gap to further reduce cost. The second module design is using more bare die (field programmable gate arrays and memory) for a much higher interconnect density but is still using existing design guidelines. It is believed that 4-mil vias are achievable in production and will be developed for future designs requiring higher density. Diffusion patterning allows a 50% reduction (4-6 mil) in via size versus traditional printed vias (10-20 mil). In combination with fine-line printing, higher interconnect density is achievable than with conventional thick film processing. Fine-line printing improvements are a result of selecting state of the art meshes and emulsions in combination with special preparations, allowing unusually good track width reduction and excellent line definition.<<ETX>>

  • Stresses in thin film metallization

    Stresses in conductors used in microelectronic interconnections are a critical processing and reliability issue. This work examines: 1) the temperature- dependent stress behavior of sputtered and electroplated silver and gold films on silicon substrates; 2) the use of wafer curvature using multiple substrates for the simultaneous determination of coefficient of thermal expansion (CTE) and modulus for thin films. The stress-temperature behavior of gold films on gallium arsenide and aluminum substrates was measured to determine its CTE and modulus. It is shown that electroplated noble metal films have lower stresses than sputtered films, due to larger grain sizes.

  • Characterization of anisotropically conductive adhesive interconnections by 1/f noise measurements

    Today there is growing interest in using anisotropically conductive adhesives (ACAs) not only for interconnections between liquid crystal displays and printed circuit boards but also in contacts conducting higher currents such as flip-chip and rigid-flexible interconnections, for example in automotive applications. 1/f noise measurements are commonly known as a diagnostic tool to investigate the lifetime of chip metallizations. Resistance fluctuations (which mean noise) are induced by electron mobility fluctuations due to, for example, scattering on moving atoms (electromigration). Another source of noise is resistance fluctuations that are dominated by the current constriction in a point contact. Both mechanisms play a role in ACA contacts. A technology to prepare anisotropically conductive interconnections with only a few conducting particles per contact to separate different failure mechanisms and to realize the noise measurements is presented. Samples manufactured in this way are exposed to current. The noise is measured before and after these damaging processes. Our measurements show that anisotropically conductive contacts exhibit a transition from a mixed film/spot contact behaviour to film dominated contacts when the gap between the contact pads is increased through the point where it surpasses the diameter of the conducting particles. After current damaging we find a noise spectrum consisting of a 1/f portion and an additional 1/f/sup 2/ component, which is relaxing during a following zero current period. The increase of noise power after damaging is significantly higher than the increase of resistance.

  • The effect of varying the Cu/Au ratio on the thermal-cycle fatigue life of 95/5 PbSn bumps

    The MICRO SWITCH Division of Honeywell adopted the IBM C4 flip chip die attach method for its underhood automotive applications in the mid to late 1970's. There has been a gradual increase in the reliability of IC-ceramic solder joints. This experiment shows the effect of the interface metallurgy on the thermal-cycle fatigue life of C4 technology. Samples are manufactured using a standard industry technique first pioneered by IBM. Included are results from initial experimentation on post processed bump limiting metallurgy (BLM), and mechanical data on two different sizes of IC with the variation of gold thickness. Assemblies were exposed to a thermal-cycle temperature range of -40/spl deg/C to 150/spl deg/C. In the initial tests, half of each wafer is placed in 1/1 concentrated H/sub 2/O/sub 2//Acetic to remove the PbSn bump and expose the BLM. The etched samples are SEM/EDS analyzed for interfacial constituents. A comparison of the interface morphologies and the thermal-cycle fatigue life are shown. These results show that for extended thermal-cycle life times (>1000) that the Cu thickness of 1.2 /spl mu/m and an Au thickness of 0.08 /spl mu/m which is reduced from the initial 0.15 /spl mu/m of our standard process is optimal. This is due to the reduced Au incorporation in the copper-tin intermetallic which produces an increase in the fatigue life and strength of the joints.

  • CFD applied to electronic systems: a review

    The application of commercial and noncommercial computational fluid dynamics (CFD) programs to systems relevant to electronics is reviewed. The following commercial programs are discussed: THEBES, FLOTHERM, FLUENT, FLOTRAN, FIDAP/ICEPAK, CFX 4 (formerly CFDS-FLOW3D), PHOENICS/HOTBOX, and STAR-CD. Notably, of the noncommercial programs, work utilizing a spectral element program originating from the Massachusetts Institute of Technology (MIT) is described. General thermofluid capabilities, user friendliness, and other peripheral aspects, such as the modeling of thermal stress/strain and dust transport are assessed. For all comparisons with measurements, agreement was found to be within 30%. No commercial CFD program appeared to be clearly superior for all applications, but FLOTHERM had the most use for realistic cooling design problems.



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