Conferences related to Sample And Hold Circuits

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2023 Annual International Conference of the IEEE Engineering in Medicine & Biology Conference (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE IAS Petroleum and Chemical Industry Committee (PCIC)

The PCIC provides an international forum for the exchange of electrical applications technology related to the petroleum and chemical industry. The PCIC annual conference is rotated across North American locations of industry strength to attract national and international participation. User, manufacturer, consultant, and contractor participation is encouraged to strengthen the conference technical base. Success of the PCIC is built upon high quality papers, individual recognition, valued standards activities, mentoring, tutorials, networking and conference sites that appeal to all.


2020 IEEE International Conference on Robotics and Automation (ICRA)

The International Conference on Robotics and Automation (ICRA) is the IEEE Robotics and Automation Society’s biggest conference and one of the leading international forums for robotics researchers to present their work.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation


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Periodicals related to Sample And Hold Circuits

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


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Most published Xplore authors for Sample And Hold Circuits

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Xplore Articles related to Sample And Hold Circuits

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Maximum and minimum voltage sample and hold circuits employing operational amplifiers composed of polycrystalline silicon thin-film transistors

2014 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), 2014

We have developed maximum and minimum voltage sample and hold circuits employing operational amplifiers (OPAMPs) composed of polycrystalline silicon (poly-Si) thin-film transistors (TFTs). It was confirmed that the maximum and minimum voltages are successfully sampled and held. It was also confirmed that the restoring ratio has a peak near a certain value of the operation frequency. We would like you ...


A novel approach for high-frequency gain-compensated sample-and-hold circuits

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems, 1992

Presents a novel approach for the design of fast and accurate sample-and-hold circuits. The proposed architecture uses two low-gain transductance amplifiers which have their outputs connected together. The two amplifiers can be operated alternatively in an open-loop configuration and in a closed-loop configuration. The structure is equivalent to a unity-gain buffer using an operation amplifier with a DC open-loop gain ...


A low-voltage high-speed high-linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits

2015 2nd International Conference on Knowledge-Based Engineering and Innovation (KBEI), 2015

In this paper, a low-voltage high-speed high-linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits is successfully designed and implemented in TSMC 0.18 μm standard digital complementary metal-oxide- semiconductor (CMOS) technology. In the proposed structure, constant capacitor of the analog bootstrapped switch is replaced with anti-parallel depletion- mode metal-oxide-semiconductor (MOS) devices. In addition to area efficiency achieved by replacing the capacitor ...


Selected sample and hold circuits for the digital-to-analog conversion process

Proceedings of IECON '93 - 19th Annual Conference of IEEE Industrial Electronics, 1993

Signal processing for industrial control or automotive applications is done mostly on the digital level. The subsequent signal reconstruction process on the analog signal level often includes sample and hold-circuits. The paper investigates amplitude, phase and group delay behavior of the exponential and the polygonal hold, points out some peculiarities in amplitude and group delay close to the Nyquist frequency, ...


Modeling neural information transfer via sample and hold circuits

IJCNN-91-Seattle International Joint Conference on Neural Networks, 1991

Summary form only given, as follows. A class of protein polymers called microtubules (MTs), thought to be responsible for information transfer at the cellular level, was modeled. Specifically, the electron transfer was modeled as taking place in a bucket brigade fashion, using a specialized matrix of sample and hold circuits to retain charge at various MT sites. A set of ...


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Educational Resources on Sample And Hold Circuits

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IEEE.tv Videos

Intelligent Systems for Deep Space Exploration: Solutions and Challenges - Roberto Furfaro
Robotics History: Narratives and Networks Oral Histories:Brian Wilcox
IEEE Custom Integrated Circuits Conference
Unique Fixtures for Characterizing Electromagnetic Properties of Materials at THz Frequencies: MicroApps 2015 - Keysight Technologies
Alice Wang - SSCS Chip Chat Podcast, Episode 6
Molecular Diagnostics for STIs - Gary Schoolnik - IEEE EMBS at NIH, 2019
Yasir Saleem: Exploitation of Social IoT for Recommendation Services - Special Session on SIoT: WF-IoT 2016
Moving into the Future with Smart Medicine: Thomas Schmitz-Rode
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
THz Transistors: Present and Future
IMS 2011 Microapps - STAN Tool: A New Method for Linear and Nonlinear Stability Analysis of Microwave Circuits
2017 IEEE Donald O. Pederson Award in Solid-State Circuits: Takao Nishitani and John S. Thompson
Starting Your Own Company - The Challenges and the Rewards
William S. Carter and Stephen Trimberger - 2018 Donald O. Pederson Award in Solid-State Circuits at IEEE ISSCC
REACH (Raising Engineering Awareness through the Conduit of History)
Multi-Level Optimization for Large Fan-In Optical Logic Circuits - Takumi Egawa - ICRC 2018
Rebooting Computing: HCI: What does the future hold for the human experience
ICASSP 2010 - Science and Technology of DSP
Interview with Takao Nishitani - IEEE Donald O. Pederson Award in Solid-State Circuits Co-Recipient 2017
Design and Comparison of Crosstalk Circuits at 7nm - Md Arif Iqbal - ICRC San Mateo, 2019

IEEE-USA E-Books

  • Maximum and minimum voltage sample and hold circuits employing operational amplifiers composed of polycrystalline silicon thin-film transistors

    We have developed maximum and minimum voltage sample and hold circuits employing operational amplifiers (OPAMPs) composed of polycrystalline silicon (poly-Si) thin-film transistors (TFTs). It was confirmed that the maximum and minimum voltages are successfully sampled and held. It was also confirmed that the restoring ratio has a peak near a certain value of the operation frequency. We would like you to propose novel applications using these circuits.

  • A novel approach for high-frequency gain-compensated sample-and-hold circuits

    Presents a novel approach for the design of fast and accurate sample-and-hold circuits. The proposed architecture uses two low-gain transductance amplifiers which have their outputs connected together. The two amplifiers can be operated alternatively in an open-loop configuration and in a closed-loop configuration. The structure is equivalent to a unity-gain buffer using an operation amplifier with a DC open-loop gain which is equal to the product of the DC gains of the two stages. Offset contributions to the output voltage are also compensated. Results of a computer simulation of a sample-and hold circuit developed for a 1.2- mu m CMOS technology are reported.<<ETX>>

  • A low-voltage high-speed high-linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits

    In this paper, a low-voltage high-speed high-linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits is successfully designed and implemented in TSMC 0.18 μm standard digital complementary metal-oxide- semiconductor (CMOS) technology. In the proposed structure, constant capacitor of the analog bootstrapped switch is replaced with anti-parallel depletion- mode metal-oxide-semiconductor (MOS) devices. In addition to area efficiency achieved by replacing the capacitor with MOS transistors, the integration of the analogue bootstrapped switch would become compatible with standard digital CMOS technologies. Circuit-level simulations show that at 25 MHz input signal and 250 MHz sampling clock frequency with 0.9Vppsupply voltage, the proposed switch performs well and provides a high linearity.

  • Selected sample and hold circuits for the digital-to-analog conversion process

    Signal processing for industrial control or automotive applications is done mostly on the digital level. The subsequent signal reconstruction process on the analog signal level often includes sample and hold-circuits. The paper investigates amplitude, phase and group delay behavior of the exponential and the polygonal hold, points out some peculiarities in amplitude and group delay close to the Nyquist frequency, compares the spectral distribution of the output signal for a sine input signal, and discusses the consequences for the implementation. The results for the exponential hold are applied to the widely used zero order hold, which (in the non-ideal case) can be considered as an exponential hold with a well defined-though comparatively small-time constant of the internal hold-capacitor charging circuit.<<ETX>>

  • Modeling neural information transfer via sample and hold circuits

    Summary form only given, as follows. A class of protein polymers called microtubules (MTs), thought to be responsible for information transfer at the cellular level, was modeled. Specifically, the electron transfer was modeled as taking place in a bucket brigade fashion, using a specialized matrix of sample and hold circuits to retain charge at various MT sites. A set of pulse transfer waveforms is given in addition to a sequence of pulse trains to describe a possible directional transfer among sites, based upon genetic, polymerization, or other effects.<<ETX>>

  • Fault modeling and testing generation for sample-and-hold circuits

    The author presents the first comprehensive study of fault modeling of the class of sample-and-hold circuits frequently used in mixed analog/digital signal processors. The faults under study consist of catastrophic faults and out-of-specification faults. Even if the faults are restricted to the passive components and MOS switches (i.e. the operational amplifiers are assumed fault-free), the effects of these faults are quite complex, especially the out-of-specification faults. For example, an incorrect value of the resistor R/sub on/ of an MOS switch and an incorrect value of the capacitor in some cases have the same faulty manifestations at the output, and may be thought of as equivalent faults. The concept of fault equivalence is validated for analog circuits. The results show that various types of faults are distinguishable, thus reducing the size of the analog fault dictionary used in further diagnosis.<<ETX>>

  • Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps

    Sample and hold circuits (SHC) form the front-end circuitry for the switched capacitance pipeline or successive approximation register A/D converter (ADC). The linearity obtained from SHC directly impacts the overall linearity obtainable from the A/D converter. In this paper we describe a new technique for the input-sampling network. Open loop gain and settling time have been optimized for maximum linearity. We also propose a novel architecture to resolve the closed loop pole-zero problems. Linearity as high as 100 dB at a clock speed of 80 MHz was achieved.

  • Transient response of sample-and-hold circuits

    The transient response of sample-and-hold circuits with parabolic approximation of switch resistance is considered. As a rule, such a law gives a maximum guaranteed duration for the transient process (acquisition time).

  • Some Remarks on the Use of Time-Varying Delay to Model Sample-and-Hold Circuits

    This note revises the so-called input delay approach to the control of sampled-data systems with nonuniform sampling, in which the sample-and-hold circuit is embedded into an analog system with a time- varying input delay. It is shown that the conservatism in calculating the maximal admissible sampling period is reduced by about 57% if the time- varying delay embedding step is omitted.

  • Sample and hold circuits for low-frequency signals in analog-to-digital converter

    Different sample and hold (S/H) circuits are introduced, analyzed and simulated in this paper. It aims to illustrate the suitable sample and hold (S/H) circuit technique that is used in low voltage operation. In addition to that, a suitable sample and hold (S/H) circuit for electrocardiogram (ECG) signal is presented. A modified versions of passive free op-amp sample and hold (S/H) circuit is discussed in order to compensate the induced error. These different sample and hold (S/H) circuits were simulated using 90nm CMOS technology on LT Spice IV. According to the simulation results, the passive free op-amp sample and hold circuit has a signal to noise and distortion ratio (SNDR) of 54.34 dB. On the other hand, the differential passive free op-amp sample and hold circuit has 56.31 dB for a 250 Hz-500 mV<sub>p-p</sub> input sinewave and ECG signals. The sampling rate is 10 KS/sec, and the supply voltage is 1V. The simulation results show that the differential passive free op-amp sample and hold (S/H) circuit is the best candidate for low-frequency signals.



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