Conferences related to Ultra-low-voltage Logic Design

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)

The conference will provide a forum for discussions and presentations of advancements inknowledge, new methods and technologies relevant to industrial electronics, along with their applications and future developments.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


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Periodicals related to Ultra-low-voltage Logic Design

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Intelligent Transportation Systems, IEEE Transactions on

The theoretical, experimental and operational aspects of electrical and electronics engineering and information technologies as applied to Intelligent Transportation Systems (ITS). Intelligent Transportation Systems are defined as those systems utilizing synergistic technologies and systems engineering concepts to develop and improve transportation systems of all kinds. The scope of this interdisciplinary activity includes the promotion, consolidation and coordination of ITS technical ...


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Most published Xplore authors for Ultra-low-voltage Logic Design

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Xplore Articles related to Ultra-low-voltage Logic Design

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Analysis of ultra-low voltage digital circuits over process variations

2012 IEEE Subthreshold Microelectronics Conference (SubVT), 2012

Ultra-low voltage electronics is a subject that introduces unique issues. Problems such as process variation adversely affect digital electronics at ultra-low voltages. Signal integrity and systematic timing strongly influence low-voltage digital designs because of the low static noise margin. Candidate solutions include Schmitt-trigger gate design and asynchronous paradigm such as the NULL Convention Logic. Four gate libraries are constructed for ...


High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2016

In this paper we propose a differential dynamic dual rail CMOS logic style for ultra-low-voltage and high-speed operation. For a supply voltage equal to 300mV using a 90nm TSMC CMOS process the speed of the proposed logic style is more than 25 times faster than traditional dual rail clocked voltage switch logic CVSL.


Ultra-low voltage digital circuit design: A comparative study

2012 IEEE Faible Tension Faible Consommation, 2012

Ultra-low voltage digital circuit is an active research area that tailors portable applications. Such applications include wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Two major goals of such systems are minimized energy consumption and improved compatibility with low-voltage power supplies and analog components. The immediate solution to achieve these goals is to reduce the supply voltage, ...


High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter

2015 IEEE Computer Society Annual Symposium on VLSI, 2015

In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and recharge devices to the clock, power supply (VDD) ...


Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV

2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A generic ultra low-voltage (ULV) CMOS design approach is presented. By applying a floating capacitor to the gate terminal of the enhanced driving transistors, obtained by using a charge injection technique, we may change the ON and OFF currents. The delay in circuits where the enhanced transistors are utilized can be reduced significantly compared to complementary CMOS. The current level ...


More Xplore Articles

Educational Resources on Ultra-low-voltage Logic Design

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IEEE.tv Videos

CASS Lecture "Deep-Subthreshold Operation of ADPLLs, Transmitters and ADCs"
IMS 2011 Microapps - Ultra Low Phase Noise Measurement Technique Using Innovative Optical Delay Lines
CIRCUIT DESIGN USING FINFETS
An Ultra-Wideband Low-Power ADPLL Chirp Synthesizer with Adaptive Loop Bandwidth in 65nm CMOS: RFIC Interactive Forum
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
BSIM Spice Model Enables FinFET and UTB IC Design
Ultra Reliable Low Latency Communication for 5G New Radio - Rapeepat Ratasuk - 5G Technologies for Tactical and First Responder Networks 2018
Low-energy High-performance Computing based on Superconducting Technology
ISEC 2013 Special Gordon Donaldson Session: Remembering Gordon Donaldson - 5 of 7 - SQUID Instrumentation for Early Cancer Diagnostics
Voltage Metrology with Superconductive Electronics
Coherent Photonic Architectures: The Missing Link? - Hideo Mabuchi: 2016 International Conference on Rebooting Computing
IEEE Sections Congress 2014: Luc Van den Hove, Wearable Medical Technology
IMS 2014: Broadband Continuous-mode Power Amplifiers
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
JUSTIN M. SHAW - IEEE Magnetics Distinguished Lecture
A Low Power High Performance PLL with Temperature Compensated VCO in 65nm CMOS: RFIC Interactive Forum
Infineon Technologies: Power Efficiency from Generation to Consumption
APEC 2011-Intersil Promo Apec 2011
Energy Efficiency of MRR-based BDD Circuits - Ozan Yakar - ICRC San Mateo, 2019
Resonant Power Supply: NXP

IEEE-USA E-Books

  • Analysis of ultra-low voltage digital circuits over process variations

    Ultra-low voltage electronics is a subject that introduces unique issues. Problems such as process variation adversely affect digital electronics at ultra-low voltages. Signal integrity and systematic timing strongly influence low-voltage digital designs because of the low static noise margin. Candidate solutions include Schmitt-trigger gate design and asynchronous paradigm such as the NULL Convention Logic. Four gate libraries are constructed for comparison between static CMOS and Schmitt-trigger gate design, and between synchronous and asynchronous logic gates. A small test circuit is implemented to measure success rate, active energy, leakage power, and threshold under process variation. Results show that process variation strongly affects ultra- low voltage electronics and that Schmitt-trigger gate design and NULL Convention Logic are effective solutions for deep subthreshold operation.

  • High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mV

    In this paper we propose a differential dynamic dual rail CMOS logic style for ultra-low-voltage and high-speed operation. For a supply voltage equal to 300mV using a 90nm TSMC CMOS process the speed of the proposed logic style is more than 25 times faster than traditional dual rail clocked voltage switch logic CVSL.

  • Ultra-low voltage digital circuit design: A comparative study

    Ultra-low voltage digital circuit is an active research area that tailors portable applications. Such applications include wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Two major goals of such systems are minimized energy consumption and improved compatibility with low-voltage power supplies and analog components. The immediate solution to achieve these goals is to reduce the supply voltage, but doing so raises the issue of operability. At low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process/voltage/temperature variations being more significant at lower voltages. This paper presents a comparative study of two circuit- and architecture-level techniques that address digital signal integrity and system timing at ultra-low voltages, i.e., Schmitt- trigger gate structure and delay-insensitive asynchronous logic. Results from test circuits show that static designs have wider dynamic range, while Schmitt-trigger designs are capable of operating at lower voltages. In addition, for static designs the synchronous circuit performs better in energy. For Schmitt-trigger design the asynchronous circuit has advantage.

  • High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter

    In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and recharge devices to the clock, power supply (VDD) and input signals. The simulation results for the designed ULV logic in a typical 90nm CMOS technology show more than 40% delay reduction. Higher speed in the lower supply voltages and robustness against process variations are the main advantages of the proposed approach in comparison to the previously reported FGULV and other ULV methods.

  • Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV

    A generic ultra low-voltage (ULV) CMOS design approach is presented. By applying a floating capacitor to the gate terminal of the enhanced driving transistors, obtained by using a charge injection technique, we may change the ON and OFF currents. The delay in circuits where the enhanced transistors are utilized can be reduced significantly compared to complementary CMOS. The current level of the transistors may be increased for high speed and decreased for low power applications. The design approach may be used to implement ultra low-voltage and high-speed digital logic and Flip-Flops. In addition, the generic technique can be used to implement multiple-valued and analog ultra low-voltage CMOS circuits. For ultra low-voltage digital applications the delay may be reduced to less than 10% compared to static CMOS. The high speed Flip-FLOP presented shows a similar increase in speed compared to conventional Flip-Flops for low supply voltages. For the analog circuit presented the increased current level is used to obtain rail-to-rail operation at higher frequencies than conventional analog circuits.

  • Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits

    This paper presents a comparative study between Tunnel-FETs (TFETs) and SOI MOSFETs for ultra-low power digital circuits targeting ultra-low voltages (below 500mV). We illustrateg a device-circuit co-design of n- and p-type Tunnel FETs leading to a good tradeoff between current leakage, effective capacitance and transistor imbalance at ultra-low V<sub>DD</sub>. TFETs and MOSFETs at 30 nm gate length are compared in terms of DC robustness, effect of transistor stacking, performance and potential for minimum-energy operation under aggressive voltage scaling.

  • Design margin elimination through robust timing error detection at ultra-low voltage

    This paper discusses a timing error masking-aware ARM Cortex M0 microcontroller system. Through in-path timing error detection, operation at the point-of-first-failure is possible without corrupting the pipeline state, effectively eliminating traditional timing margins. Error events are flagged and gathered to allow dynamic voltage scaling. The error-aware microcontroller was implemented in a 40nm CMOS process and realizes ultra-low voltage operation down to 0.29V at 5MHz consuming 12.90pJ/cycle, or a MEP of 11.11pJ/cycle at 7.5MHz. Measurements show the in situ approach is ideal to overcome traditional SS corner design margins (75% energy reduction). Additionally it overcomes the limitations introduced by replica path based techniques typically plagued by intradie variations (8% reduction).

  • Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives

    In Part II of this paper, the potential of tunnel FETs (TFETs) for ultra-low voltage (ULV)/ultra-low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of appropriate reference circuits. Critical issues arising at ultra-low voltages are analyzed, including static robustness of TFET logic gates, performance degradation, and sensitivity to process variations. Guidelines to design ultra-low energy standard cell libraries are derived. The minimum energy point is analyzed in a wide range of conditions, and guidelines for microarchitectural optimization for ultra-low energy are introduced. Voltage scalability of static RAM memories is also analyzed as main limitation to aggressive voltage scaling of very large scale integration (VLSI) systems, and improved precharge schemes are introduced to reduce leakage. The impact of variations of the main device parameters on VLSI digital circuits is investigated to identify the most critical variations that need to be controlled at process level. This investigation permits to understand the potential of TFETs and their advantages over traditional devices within a unitary framework that is based on fair design and comparison from device to circuit level, as well as to develop clear design perspectives in the context of ULV/ULP VLSI digital circuits.

  • Low Voltage Design against Power Analysis Attacks

    In this paper we promote the ultra low voltage (ULV) gate to replace either partly or entirely the encryption block of a design to withstand power analysis attack. Some of the keywords in this work are: differential power analysis (DPA), low voltage (LV), ultra low voltage (ULV), floating-gate (FG) and supply current analysis.

  • Static ultra low voltage CMOS logic

    In this paper we examine a quasi static and a static ultra low-voltage precharge CMOS logic. The static ultra low-voltage logic can be used to design high speed and energy efficient CMOS circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate can be reduced to less than 10% compared to a static complementary gate.



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IEEE Guide for Control of Small Hydroelectric Power Plants



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