80 resources related to Memory Modules
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No organizations are currently tagged "Memory Modules"
The ITherm Conference series is the leading international venue for scientific and engineering exploration of thermal, thermomechanical, and emerging technology issues associated with electronic devices, packages, and systems.
ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.
SoutheastCon is the annual Region 3 conference that brings together engineering professionals, students, and volunteers for a weekend of technical presentations, meetings, student competitions, and volunteer education.
The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared among the organizing entities. This collaboration will be oriented towards advanced research in adaptive systems which constitutes the highlights of the NEWCAS conference, but also areas related to analog and digital signal processing, low power consumption, and circuits and systems designs. The topics include, but are not limited to: Computer architecture and memories, Analog circuit design, Digital and mixed-signal circuit design, RF circuit design, mm-Wave circuits, Microsystems, sensors and actuators, Test and verification, Communication, microwaves and RF, Technology Trends, Data and signal processing, Neural networks and artificial vision, CAD and design tools, Low-Power circ. & syst. techniques, Imaging & image sensors, Embedded hand-held devices, Biomed. circuits & systems, Energy Harvesting / Scavenging
The world's premiere conference in MEMS sensors, actuators and integrated micro and nano systems welcomes you to attend this four-day event showcasing major technological, scientific and commercial breakthroughs in mechanical, optical, chemical and biological devices and systems using micro and nanotechnology.The major areas of activity in the development of Transducers solicited and expected at this conference include but are not limited to: Bio, Medical, Chemical, and Micro Total Analysis Systems Fabrication and Packaging Mechanical and Physical Sensors Materials and Characterization Design, Simulation and Theory Actuators Optical MEMS RF MEMS Nanotechnology Energy and Power
No periodicals are currently tagged "Memory Modules"
2018 IEEE International Conference on Computational Electromagnetics (ICCEM), 2018
In this paper, a simulation methodology considering signal integrity (SI) and power integrity (PI) from the chip, package, and board levels of a double- data-rate three (DDR3) memory module is presented. For SI issues, the chip- package-board simulation indicates how to improve eye diagram by eliminating non-ideal effects of the most crucial part of the channel. For PI issues, the ...
2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019
An advanced 3D Multi-stack (MUST) system integration technology, 3D MUST-in- MUST (3D-MiM) fan out package, has been developed as next generation wafer- level fan-out package technology. 3D-MiM technology utilizes a more simplified architecture which eliminates BGAs between packages for system-level performance, power and form-factor (PPA) purpose. This technology also makes use of a modularized approach for both design and integration ...
Dynamic System Reliability: Modeling and Analysis of Dynamic and Dependent Behaviors, None
A hierarchical system (HS) is a system whose underlying architecture can be characterized by multiple layers, with each layer housing different modules and/or components. In an HS, the failure behavior of an upper level often relies on the failure behavior of its lower level. This chapter introduces the model of representing the multilevel imperfect coverage behavior and methods of considering ...
2018 International Conference on Signals and Systems (ICSigSys), 2018
Short Word Length (SWL) DSP systems offer good performance as they process less data-typically up to three bits. Short Word Length systems may be designed using the FPGAs. FPGAs come with many built-in primitives like Look- up tables, Flip-flops, additional Carry logic, Memories and DSP elements. All these primitives give alternative approaches for FPGA based system design. This paper presents ...
2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2018
In this paper, a unique technical approach is presented to accurately analyze and optimize the address bus of an onboard DDR4 memory module by taking power plane induced noise and thermal effect simultaneously in the analysis. For high-speed digital designers, designing data channel in DDR4 memory is always challenging due to high data rates of 3.2GB/s per data signal at ...
Patrizio Vinciarelli, Newell Award: APEC 2019
IMS 2012 Special Sessions: The Evolution of Some Key Active and Passive Microwave Components - N. J. Kolias
IMS MicroApps: Silicon Technology Solutions for Wireless Front End Modules
IMS 2014: LNA Modules for the WR4 (170-260 GHz) Frequency Range
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017
Ted Berger: Far Futures Panel - Technologies for Increasing Human Memory - TTM 2018
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Impact of Linearity and Write Noise of Analog Resistive Memory: IEEE Rebooting Computing 2017
Non-Volatile Memory Array Based Quantization - Wen Ma - ICRC San Mateo, 2019
Array storing and retrieval
High-Bandwidth Memory Interface Design
Compressive Sensing Tutorial: A Game Changing Technology for Energy Efficient IoT Sensor Networks: WF-IoT 2016
Transphorm: GaN Champions
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth
IRDS: Lithography - Mark Neisser at INC 2019
Memory Centric Artificial Intelligence - Damien Querlioz at INC 2019
RNSnet: In-Memory Neural Network Acceleration Using Residue Number System - Sahand Salamat - ICRC 2018
In this paper, a simulation methodology considering signal integrity (SI) and power integrity (PI) from the chip, package, and board levels of a double- data-rate three (DDR3) memory module is presented. For SI issues, the chip- package-board simulation indicates how to improve eye diagram by eliminating non-ideal effects of the most crucial part of the channel. For PI issues, the SI/PI co-simulation is concerned with the power distribution network (PDN) and the distribution of decoupling capacitors (De-Caps). In addition, the optimized set of de-caps by simulation provides a cost-effect way to meet the desired target impedance for acceptable simultaneous switching noise (SSN) generated in PDN due to I/O switching. Finally, the co-simulation methodology can indicate SI/PI problems before IC tape-out and reduce circuit design cycle as well.
An advanced 3D Multi-stack (MUST) system integration technology, 3D MUST-in- MUST (3D-MiM) fan out package, has been developed as next generation wafer- level fan-out package technology. 3D-MiM technology utilizes a more simplified architecture which eliminates BGAs between packages for system-level performance, power and form-factor (PPA) purpose. This technology also makes use of a modularized approach for both design and integration flow to improve design flexibility and integration efficiency. Known-good pre-stacked memory cube and/or logic-memory cubes are fabricated by leveraging the established integrated fan-out technology platform (InFO) in tools, materials, design rules, and processes to shorten development cycle time and achieve cost effectiveness. Two 3D-MiM fan-out examples are presented in this paper. The first 3D-MiM package integrates a SoC with 16 memory chips in a 15x15 mm2 footprint with 0.5 mm package height (final BGA included) for mobile application. The other 3D-MiM package integrates 8 SoCs with 32 memory chips in a 43x28 mm2 footprint to mimic a system integration of multiple logic cores and multiple memory chips for HPC applications.
A hierarchical system (HS) is a system whose underlying architecture can be characterized by multiple layers, with each layer housing different modules and/or components. In an HS, the failure behavior of an upper level often relies on the failure behavior of its lower level. This chapter introduces the model of representing the multilevel imperfect coverage behavior and methods of considering the behavior in the reliability analysis of nonrepairable and repairable HSs. The modular imperfect coverage model (MIPCM) was first introduced to analyze effects of the multiple levels of uncovered failure (UF) modes for components in HSs. The MIPCM extends the traditional one‐level imperfect coverage model by consideringmultiple levels of UFs resulting from the layered recovery of HSs. Based on fault tree modeling, the hierarchical and separable methodology is presented for addressing effects of MIPCM in the reliability analysis of nonrepairableHSs and availability analysis of repairable HSs.
Short Word Length (SWL) DSP systems offer good performance as they process less data-typically up to three bits. Short Word Length systems may be designed using the FPGAs. FPGAs come with many built-in primitives like Look- up tables, Flip-flops, additional Carry logic, Memories and DSP elements. All these primitives give alternative approaches for FPGA based system design. This paper presents a way to use the Look-up tables to design three bit (3×3) constant coefficient unsigned integral multiplier for Short Word Length DSP systems. Besides, the feasibility of using Block ram and DSP elements for Short Word Length DSP system (multiplier) is also carried out as an alternative implementation approach. Result suggests the proposed way be the better one when compared with other two implementations.
In this paper, a unique technical approach is presented to accurately analyze and optimize the address bus of an onboard DDR4 memory module by taking power plane induced noise and thermal effect simultaneously in the analysis. For high-speed digital designers, designing data channel in DDR4 memory is always challenging due to high data rates of 3.2GB/s per data signal at a low-voltage of 1.2V. The design is simulated at 1.6 Gbps that is the highest DDR4 switching rate in a configuration containing four memory devices. It is important to catch SI and PI problems at an early stage in design that requires fast and accurate signal integrity analysis for address bus. To maximize eye opening, address bus interconnects impedance optimization is carried out. DDR4 power plane and address signals are analyzed using PI-SI solver that is based on full-wave electromagnetic simulation, then the transient simulation is performed on combined PI data of power plane and address bus. The coupling of simultaneous switching noise (SSN), power plane jitter and thermal effects on DDR4 address bus signals are accounted in power and thermal-aware signal integrity analysis using PIPro signal integrity solution.
Development of LSI targeting artificial intelligence (AI) has accelerated, some chips have been used and are commercially available in a number of applications. LSI capable of performing arithmetic operation for deep learning, etc., at low power and high speed is crucial for achieving more sophisticated AI. Power consumption is increasing significantly owing particularly to the practical use of AI, and power reduction techniques are urgently necessary.
This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.
This paper evaluates the optimal scale of datacentre (DC) resource disaggregation for composable DC infrastructures and investigates the impact of present day silicon photonics technologies on the energy efficiency of different composable DC infrastructures. We formulated a mixed integer linear programming (MILP) model to this end. Our results show that present day silicon photonics technologies enable better network energy efficiency for rack-scale composable DCs compared to pod-scale composable DCs despite reported similarities in CPU and memory resource power consumption.
Transparent Memory-Compression (TMC) allows the system to obtain the bandwidth benefits of memory compression in an OS-transparent manner. Unfortunately, prior designs for TMC (MemZip) rely on using non-commodity memory modules, which can limit their adoption. We show that TMC can be implemented with commodity memories by storing multiple compressed lines in a single memory location and retrieving all these lines in a single memory access, thereby increasing the effective memory bandwidth. TMC requires metadata to specify the compressibility and location of the line. Unfortunately, even with dedicated metadata caches, maintaining and accessing this metadata incurs significant bandwidth overheads and causes slowdown. Our goal is to enable TMC for commodity memories by eliminating the bandwidth overheads of metadata accesses. This paper proposes PTMC (Practical and Transparent Memory- Compression), a simple design for obtaining bandwidth benefits of memory compression while relying only on commodity (nonECC) memory modules and avoiding any OS support. Our design uses a novel inline-metadata mechanism, whereby the compressibility of the line can be determined by scanning the line for a special marker word, eliminating the overheads of metadata access. We also develop a low-cost Line Location Predictor (LLP) that can determine the location of the line with 98% accuracy and a dynamic solution that disables compression if the benefits of compression are smaller than the overheads. Our evaluations show that PTMC provides a speedup of up to 73%, is robust (no slowdown for any workload), and can be implemented with a total storage overhead of less than 300 bytes.
PASM, a large-scale multimicroprocessor system being designed at Purdue University for image processing and pattern recognition, is described. This system can be dynamically reconfigured to operate as one or more independent SIMD and/or MIMD machines. PASM consists of a parallel computation unit, which contains N processors, N memories, and an interconnection network; Q microcontrollers, each of which controls N/Q processors; N/Q parallel secondary storage devices; a distributed memory management system; and a system control unit, to coordinate the other system components. Possible values for N and Q are 1024 and 16, respectively. The control schemes and memory management in PASM are explored. Examples of how PASM can be used to perform image processing tasks are given.
No standards are currently tagged "Memory Modules"