Memory Array Organizations
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
Multimedia technologies, systems and applications for both research and development of communications, circuits and systems, computer, and signal processing communities.
the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.
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Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...
Physics, medicine, astronomy—these and other hard sciences share a common need for efficient algorithms, system software, and computer architecture to address large computational problems. And yet, useful advances in computational techniques that could benefit many researchers are rarely shared. To meet that need, Computing in Science & Engineering (CiSE) presents scientific and computational contributions in a clear and accessible format. ...
The design and manufacture of consumer electronics products, components, and related activities, particularly those used for entertainment, leisure, and educational purposes
2008 Symposium on VLSI Technology, 2008
We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; ...
IEEE Transactions on Computers, 2016
As the descendant of spin-transfer random access memory (STT-RAM), racetrack memory technology saves data in magnetic domains along nanoscopic wires. Such a unique structure can achieve unprecedentedly high storage density meanwhile inheriting the promising features of STT-RAM, such as fast access speed, non- volatility, zero standby power, hardness to soft errors, and compatibility with CMOS technology. Moreover, the recent success ...
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
This paper describes a novel architecture for a content-addressable memory core which is intended to be included in a Field-Programmable Gate Array or an Embedded Programmable Logic Core. Compared to a standard content-addressable memory, our architecture allows for arbitrary data and tag widths; this flexibility is vital in FPGA applications, since the size of the data and tag fields are ...
IEEE Transactions on Multi-Scale Computing Systems, 2016
New nonvolatile memory devices can overcome the high-energy consumption, volatility, and density scaling limit of dynamic RAM (DRAM). With these advantages, next-generation nonvolatile memory devices can use both working memory and persistent storage simultaneously. In this study, we horizontally arrange DRAM, phase change memory (PCM), and flash memories as a single compound layer of working and storage space for a ...
2012 41st International Conference on Parallel Processing Workshops, 2012
Data organization for matrices and arrays in memory has been extensively studied since the early 70's and until the mid 90's - the vector computers golden age. But this old SIMD model seems more topical than ever, as shown by the use of GPU in high performance computers or the architecture of the Nec SX-9. Such memory organization should then ...
Non-Volatile Memory Array Based Quantization - Wen Ma - ICRC San Mateo, 2019
Array Insertion and Deletion
The Memory of Cars Talk by Tom Coughlin
Array Transversing through strings
Concept of Arrays
A Recurrent Crossbar of Memristive Nanodevices Implements Online Novelty Detection - Christopher Bennett: 2016 International Conference on Rebooting Computing
Standards Development Organizations
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Micro-Apps 2013: Rapid Simulation of Large Phased Array T/R Module Networks
A 30-MHz-to-3-GHz CMOS Array Receiver with Frequency and Spatial Interference Filtering for Adaptive Antenna Systems: RFIC Industry Showcase
Ted Berger: Far Futures Panel - Technologies for Increasing Human Memory - TTM 2018
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Large Motion Range Magnet Levitation Using a Planar Array of Coils
A 39GHz 64-Element Phased-Array CMOS Transceiver - Yun Wang - RFIC 2019 Showcase
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; fast source-side injection programming (10-20 us); fast tunnel erase into the gate; and robust high temperature data retention for both uncycled and cycled arrays. Results presented here with focus on the array operation demonstrate the maturity of this technology for implementation into consumer, industrial, and automotive microcontrollers.
As the descendant of spin-transfer random access memory (STT-RAM), racetrack memory technology saves data in magnetic domains along nanoscopic wires. Such a unique structure can achieve unprecedentedly high storage density meanwhile inheriting the promising features of STT-RAM, such as fast access speed, non- volatility, zero standby power, hardness to soft errors, and compatibility with CMOS technology. Moreover, the recent success in planar racetrack nanowire promised its fabrication feasibility and continuous scalability. In this paper, we investigate the design and optimization of racetrack memory as last-level cache by embracing design considerations across multiple abstraction layers, including the cell design, the array structure, the architecture organization, and the data management. The cross-layer optimization makes racetrack memory based last-level cache achieve 6.4 × reduction in area, 25 percent enhancement in system performance, and 62 percent saving in energy consumption, compared to STT-RAM cache design. Its benefit over SRAM technology is even more significant.
This paper describes a novel architecture for a content-addressable memory core which is intended to be included in a Field-Programmable Gate Array or an Embedded Programmable Logic Core. Compared to a standard content-addressable memory, our architecture allows for arbitrary data and tag widths; this flexibility is vital in FPGA applications, since the size of the data and tag fields are not known when the FPGA is manufactured.
New nonvolatile memory devices can overcome the high-energy consumption, volatility, and density scaling limit of dynamic RAM (DRAM). With these advantages, next-generation nonvolatile memory devices can use both working memory and persistent storage simultaneously. In this study, we horizontally arrange DRAM, phase change memory (PCM), and flash memories as a single compound layer of working and storage space for a memory-disk integrated system (MDIS). The MDIS architecture consists of a static data buffer, DRAM/PCM/Flash hybrid array, and its associated MDIS management module. The static data buffer is placed between the last-level cache and DRAM/PCM/Flash hybrid array to reduce the performance gap. In the DRAM/PCM/Flash hybrid array, DRAM space and a portion of PCM space are used for dynamic data, and the remaining portion of PCM space and flash memory are used for static data including program text and data segments. Based on our simulation results, dynamic access latency of a dynamic area with 128 MB DRAM of space is faster than the MDIS with a PCM-only array model by approximately 5.5 times. Furthermore, the results show that the total execution time of our proposed model with 128-MB DRAM space improves speed by 4.3 times compared to conventional memory-storage system, respectively.
Data organization for matrices and arrays in memory has been extensively studied since the early 70's and until the mid 90's - the vector computers golden age. But this old SIMD model seems more topical than ever, as shown by the use of GPU in high performance computers or the architecture of the Nec SX-9. Such memory organization should then be considered again in order to access efficiently data structures for high performance computations. However in almost all existing studies, the assumptions made were unrealistic: the memory model was incorrect. In fact, the memory structure was assumed to be linear (i.e. all banks identically accessible by bus(ses)), which is not the case due to the large number of memory banks (up to 32768 in a Nec SX-9). Indeed, there is nothing to be gained from connecting all the banks to one bus, and supplying one bus per bank is clearly not feasible. In order to solve this problem, architects use to structure memory in 2 (or more) dimensions: memory is organized in a number of sections, each section being composed of several banks. The problem is that classical schemes do not avoid conflicts on both the banks and the sections. In this paper, we will introduce a simple way to adapt any existing classical scheme to real memory organization: Isomorphic Recursive Splitting (IRS). The few existing works are presented, and the general theory of recursive splitting is defined. We also show, using two examples, how this model can be applied very easily and at no extra cost.
Beam steering unit (BSU) is responsible for steering of the beam in Phased Array Radar  based on beam parameters it will shift the beam from one position to other position as directed by the radar Controller. The control logic of the unit is modelled in MATLAB, Simulated in Simulink and implemented in Hardware description language. The architecture of BSU consists of Single Board Computer (SBC) and an indigenously developed Array Interface Card (AIC). SBC will receive the beam Parameter from Radar Controller and calculates the Phase gradients and phase commands based on the different tables like standard table, collimation table, and Phase command table. The AIC is having a control logic, which is residing in an FPGA . The AIC will interact with the SBC for receiving the phase command, Row number and column number of the phase shifters in the phased array. The control logic will decode the data into suitable format and converts into serial format for loading the data into phase shifters. The data will be loaded serially in each sector and parallel in other sectors of the antenna. With this design method the loading time achieved is 2.2msec. This unit can be used for different phased arrays  with varying antenna dimensions.
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and flash-based SSDs. Realizing this potential will require significant changes to the way systems interact with storage devices as well as a rethinking of the storage devices themselves. This paper describes the architecture of a prototype PCIe-attached storage array built from emulated PCM storage called Moneta. Moneta provides a carefully designed hardware/software interface that makes issuing and completing accesses atomic. The atomic management interface, combined with hardware scheduling optimizations, and an optimized storage stack increases performance for small, random accesses by 18x and reduces software overheads by 60%. Moneta array sustain 2.8 GB/s for sequential transfers and 541 K random 4 KB IO operations per second (8x higher than a state-of-the-art flash-based SSD). Moneta can perform a 5f 2-byte write in 9 us (5.6x faster than the SSD). Moneta provides a harmonic mean speedup of 2.1x and a maximum speed up of 9x across a range of file system, paging, and database workloads. We also explore trade-offs in Moneta's architecture between performance, power, memory organization, and memory latency.
This DRAM macro is suitable for a memory generator implementation. The article shows the expandable floor layout scheme (EFLS) of the DRAM macros. A macro architecture that consists of several banks has a disadvantage that the macro size becomes large, because each bank has peripheral circuits for independent operation. The EFLS eliminates this redundancy by sharing the peripheral circuits among the expansion units of the memory array. Two types of floor layouts are supported by EFLS. One is simple I/O type. The other is doubled I/O type. In both of the arrangements, a DRAM macro is formed by combination of 1 Mb memory array segments and peripheral blocks. Each block is manually designed so the macro size is minimized when all the blocks are combined together. Peripheral circuits that can be shared among 1 Mb segments are placed in the peripheral blocks to save the area.
Embedded memories currently occupy more than 50% of the chip area for typical SOC integrated circuits. Defects in memory arrays can therefore significantly degrade manufacturing yield. In such a setting, repairable embedded memories are desirable because they help improve the memory array yield of an IC. We have developed an array yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-random fault bit-maps, which are generated based on memory area, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.
This paper describes a memory efficient array architecture with data-rings for the 3-step hierarchical search block-matching algorithm (3SHS). With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify control scheme and reduce latency, respectively. In addition, we utilize the three-half-search- area scheme and circular addressing method to reduce external memory access and memory size, respectively. The results demonstrate that the array architecture with a memory efficient scheme requires a smaller memory size and low I/O bandwidth. It also provides a high normalized throughput solution for the 3SHS.
This is a full-use standard, a revision of ISO/IEC 13213:1994; its scope reflects accumulated experience with the CSR architecture since it was first promulgated as a standard in 1991. In the intervening years, two bus standards, Scaleable Coherent Interface (SCI), IEEE Std 1596-199x, and Serial Bus, IEEE Std 1394-1995, have been the source of most practical implementation experience. The revised ...
Modify the present FGA standard to include floating gate flash" EEPROM's that use Fowler-Nordheim tunneling and/or hot electron injection programming techniques. Hot electron injection EPROM's are included for completeness."