IEEE Organizations related to Design Tools

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Conferences related to Design Tools

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2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE Frontiers in Education Conference (FIE)

The Frontiers in Education (FIE) Conference is a major international conference focusing on educational innovations and research in engineering and computing education. FIE 2019 continues a long tradition of disseminating results in engineering and computing education. It is an ideal forum for sharing ideas, learning about developments and interacting with colleagues inthese fields.


2020 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM)

All topics related to engineering and technology management, including applicable analytical methods and economical/social/human issues to be considered in making engineering decisions.


2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC)

The 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2020) will be held in Metro Toronto Convention Centre (MTCC), Toronto, Ontario, Canada. SMC 2020 is the flagship conference of the IEEE Systems, Man, and Cybernetics Society. It provides an international forum for researchers and practitioners to report most recent innovations and developments, summarize state-of-the-art, and exchange ideas and advances in all aspects of systems science and engineering, human machine systems, and cybernetics. Advances in these fields have increasing importance in the creation of intelligent environments involving technologies interacting with humans to provide an enriching experience and thereby improve quality of life. Papers related to the conference theme are solicited, including theories, methodologies, and emerging applications. Contributions to theory and practice, including but not limited to the following technical areas, are invited.


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Periodicals related to Design Tools

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Xplore Articles related to Design Tools

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Efficient implementation of FPGA based on Vivado High Level Synthesis

2016 2nd IEEE International Conference on Computer and Communications (ICCC), 2016

The Xilinx Vivado High Level Synthesis (HLS) transforms a C specification into a register transfer level (RTL) implementation that can be synthesized into a Xilinx field programmable gate array (FPGA). It refers to the automatic integrated initially with C, C ++ or System C language to describe digital designs. Using HLS to explore all possibilities, analysis and performance characteristics of ...


Analysis of darlington pair amplifier at 90nm technology

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

The demand of transistors is rising in today's communication system having high data rate. Transistors are used in many applications where high gain is needed by using very low frequency. In today's communication system amplifier is used in many applications such as low noise amplifier, broadband mixer, distributed amplifier, power amplifier etc. The pair amplifier satisfy all parameters which is ...


Towards a guided design flow for heterogeneous reconfigurable architectures

2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015

In this work we present a concept of an architecture design flow for heterogeneous reconfigurable architectures. We have a special focus on high flexibility regarding the architecture design. We cover architectures from fine-grained island-style FPGAs and heterogeneous hierarchical structures through to coarse-grained reconfigurable architectures (CGRAs). Our goal is to make the development and optimization of reconfigurable architectures more efficient and ...


Makespan as a design tool for CMS design

2015 International Conference on Emerging Technologies (ICET), 2015

Industries have to cope with millions of parts for production on daily basis. Scheduling of those parts for production is a complex process. Parts having properly scheduled processing rarely get delayed and therefore generally delivered on time. Cellular Manufacturing System (CMS) is a proficient production system and can be used as an effective replacement of Batch type manufacturing. Cell Formation ...


Finite-Element Model-Based Design Synthesis of Axial Flux PMBLDC Motors

IEEE Transactions on Applied Superconductivity, 2016

This paper discusses the design synthesis of a permanent-magnet brushless dc (PMBLDC) machine using a finite-element (FE) model. This work differentiates itself from the past studies by following a synthesis approach, in which many designs that satisfy the performance criteria are considered instead of a unique solution. The designer can later select a design, based on comparing parameters of the ...


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Educational Resources on Design Tools

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IEEE-USA E-Books

  • Efficient implementation of FPGA based on Vivado High Level Synthesis

    The Xilinx Vivado High Level Synthesis (HLS) transforms a C specification into a register transfer level (RTL) implementation that can be synthesized into a Xilinx field programmable gate array (FPGA). It refers to the automatic integrated initially with C, C ++ or System C language to describe digital designs. Using HLS to explore all possibilities, analysis and performance characteristics of the area, and finalize a program to implement algorithms on FPGA chip. An example of a filter in this paper described the use of HLS to implement on FPGA quickly and efficiently.

  • Analysis of darlington pair amplifier at 90nm technology

    The demand of transistors is rising in today's communication system having high data rate. Transistors are used in many applications where high gain is needed by using very low frequency. In today's communication system amplifier is used in many applications such as low noise amplifier, broadband mixer, distributed amplifier, power amplifier etc. The pair amplifier satisfy all parameters which is required by today's technology such as-high speed transmission efficiency, less power consumption and less circuitrary to be used pair is used in advanced version of small signal amplifier with additional biasing resistance which improves voltage gain and widening of bandwidth. It also removes poor frequency response of pair amplifier at higher frequency. In this paper, cadence software is used to study the circuit of two-stage amplifier. In this paper after adding biasing resistance in emitter terminal of first transistor we can increase the voltage gain, current gain, output current and output voltage of pair amplifier. GPDK 90nm technology is used in this paper.

  • Towards a guided design flow for heterogeneous reconfigurable architectures

    In this work we present a concept of an architecture design flow for heterogeneous reconfigurable architectures. We have a special focus on high flexibility regarding the architecture design. We cover architectures from fine-grained island-style FPGAs and heterogeneous hierarchical structures through to coarse-grained reconfigurable architectures (CGRAs). Our goal is to make the development and optimization of reconfigurable architectures more efficient and convenient. Therefore our design flow includes a graphical architecture editor, which allows the user to adapt the global design structure as well as the detailed implementation of the logic blocks. An analysis tool gives the user a statistical feedback about the resource utilization of the architecture under development for a given set of benchmark applications to allow a directed exploration and optimization. We describe the envisioned design flow and compare it to a manual design flow. Finally we present the parts of the toolset that are already operational and describe how we are planning to implement the remaining tools.

  • Makespan as a design tool for CMS design

    Industries have to cope with millions of parts for production on daily basis. Scheduling of those parts for production is a complex process. Parts having properly scheduled processing rarely get delayed and therefore generally delivered on time. Cellular Manufacturing System (CMS) is a proficient production system and can be used as an effective replacement of Batch type manufacturing. Cell Formation (CF) is the fundamental part of Cell design and its effectiveness is checked using a performance index called Grouping Efficacy (GE).Part scheduling is very rarely used as a design tool for Cell Formation Problem (CFP). A software based solution is developed in this research to solve CFP by applying Genetic Algorithm (GA), which is an Artificial Intelligence (AI) technique. The uniqueness of this approach is that it presents an integrated approach for grouping parts into families and machines into cells using Makespan as the performance factor. Results show that minimizing the Make span maximizes the GE.

  • Finite-Element Model-Based Design Synthesis of Axial Flux PMBLDC Motors

    This paper discusses the design synthesis of a permanent-magnet brushless dc (PMBLDC) machine using a finite-element (FE) model. This work differentiates itself from the past studies by following a synthesis approach, in which many designs that satisfy the performance criteria are considered instead of a unique solution. The designer can later select a design, based on comparing parameters of the designs, which are critical to the application that the motor will be used for. The presented approach makes it easier to define constraints for a design synthesis problem. A detailed description of the setting up of an FE-based design synthesis problem, starting from the definition of design variables, the FE model of the machine, how the design synthesis is carried out, and to how a design is finalized from a set of designs that satisfy the performance criteria, is included in this paper. The proposed synthesis program is demonstrated by designing a segmented axial torus PMBLDC motor for an electric two-wheeler.

  • A partition level floorplan method based on data flow analysis for physical design of digital IC

    This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence company P&R tool innovus to make floorplan, and takes a X86 CPU's south bridge design for example to introduce how to use this method to guide floorplan in detail. This method is more effective to improve the quality of floorplan for advanced process technology and high speed IC design.

  • Using www.sigma-delta.de to rapidly obtain ELD compensated CT ΣΔ modulators

    For two decades, Excess-Loop-Delay (ELD) is known to degrade the performance of continuous-time (CT) ΣΔ A/D converters. Many methods have been proposed to compensate for this effect, but for their implementation sophisticated knowledge in loop-filter design is necessary. The web-based design tool for CT ΣΔ modulators www.sigma-delta.de offers a straightforward integration of commonly used ELD compensation techniques in an early stage of the design process without the need of in depth knowledge of ΣΔ loop-filters. As the tool uses a heuristic search, based on a genetic algorithm within a parallel implementation on a GPU, it provides results with a very short response time. This paper presents the compensation techniques which are commonly implemented within the state of the art and shows their automatic application on architectural level by the design tool. Exemplary modulators are created and evaluated in a circuit level simulator. Further, the calculation of device parameters for a circuit-level simulator model, based on the coefficients obtained by the tool, is illustrated. Thereby, the usage of the developed and publicly available design tool for CT ΣΔ modulator is practically shown.

  • Designing CT ΣΔ modulators with www.sigma-delta.de

    Due to a high performance and its inherent filtering capabilities, continuous- time (CT) ΣΔ modulators are the state-of-the-art for many different applications. In this demo, it is shown how to use www.sigma-delta.de for the design of these modulators. Moreover, the visitors are assisted to try the tool themselves on their own devices (e.g. notebooks, tablets, smartphones).

  • A Domain-Specific Modeling Specification of Visual Instructional Design Languages: A Moodle Experimentation

    Despite of the growing development of learning technologies into education, designing learning scenarios and exploiting them for setting up a learning situation is still a complex task. The Visual Instructional Design Languages (VIDL) and their dedicated graphical editors have been identified as important conceptual tools for achieving more creative design solutions within a design process. In this article we propose the application of Domain-Specific Modeling tools for specifying and developing VIDLs and editors dedicated to specific Learning Management Systems. An experimentation concerning the Moodle LMS is illustrated and discussed.

  • Special session on architectures and design tools for secure embedded systems

    Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. The pervasive diffusion of embedded and cyberphysical systems connected to form the internet of things brings new security challenges. These devices are usually deployed in a hostile environment, where an attacker could easily have physical access, and their life span can be pretty long, thus posing the problem of long term security. Yet, security functionalities should fit the tight area and energy budget available in these devices. To address these challenges, researchers are investigating several research directions, including novel constructions withstanding future attacks carried out by quantum computational power, novel and more powerful physical attacks and new approaches to defeat them. It is thus of crucial importance that designers of embedded systems are aware of the most important security challenges which need to be addressed during design and that they have the proper basic blocks and tools to solve them in a correct and effective way. This special session covers challenges and opportunities related with design and deployment of secure embedded systems in several platforms. Talks in the session will present more targeted side channel attacks, more efficient architectures for implementing elliptic curve cryptography (ECC) and number theoretic transform (NTT), a crucial block for implementing quantum resistant algorithms, and will summarize current research effort in secure processors design and in the use of reconfigurable architectures for secure applications.



Standards related to Design Tools

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