Conferences related to Magnetic Memory Designs

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.


2020 IEEE Industry Applications Society Annual Meeting

The Annual Meeting is a gathering of experts who work and conduct research in the industrial applications of electrical systems.


2020 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2005 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2006 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2007 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2008 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2009 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics,motion analysis and physics-based vision.

  • 2010 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics, motion analysis and physics-based vision.

  • 2011 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Sensors Early and Biologically-Biologically-inspired Vision, Color and Texture, Segmentation and Grouping, Computational Photography and Video

  • 2012 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Topics of interest include all aspects of computer vision and pattern recognition including motion and tracking,stereo, object recognition, object detection, color detection plus many more

  • 2013 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2014 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. Main conference plus 50 workshop only attendees and approximately 50 exhibitors and volunteers.

  • 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    computer, vision, pattern, cvpr, machine, learning

  • 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conferenceand 27co-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students,academics and industry.

  • 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and severalco-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students, academics and industry researchers.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 59th IEEE Conference on Decision and Control (CDC)

The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.



Periodicals related to Magnetic Memory Designs

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.



Most published Xplore authors for Magnetic Memory Designs

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Xplore Articles related to Magnetic Memory Designs

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Magnetoelectric Random Access Memory-Based Circuit Design by Using Voltage-Controlled Magnetic Anisotropy in Magnetic Tunnel Junctions

IEEE Transactions on Nanotechnology, 2015

We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory applications. We present and discuss specifically two applications, magnetoelectric random access memory (MeRAM) and ternary content-addressable memory (TCAM). The MEJ differs from a magnetic tunnel junction (MTJ) in that electric field is used to induce switching in lieu of ...


Magnetic Random Accessible Memory Based Magnetic Content Addressable Memory Cell Design

IEEE Transactions on Magnetics, 2010

In this paper, we present a novel magnetic content addressable memory (MCAM) cell architecture. The proposed MCAM cell consists of four magnetic tunneling junction devices (MTJs). All previously proposed MCAM cell designs require both magnets of MTJ to be programmable. Such requirement poses a great challenge on device fabrication. This paper describe a new design based on conventional MTJs used ...


Design of nonvolatile memory based on magnetic tunnel junction for special electronic systems

East-West Design & Test Symposium (EWDTS 2013), 2013

Description of non-volatile memory based on magnetic tunnel junction is presented. A dynamic Verilog-A behavioral model and a Spice macro-model of the single memory cell is described. The advantages of the proposed models is demonstrated on a next generation revolutionary Magnetic Random Access Memory (MRAM) which we offer to implement on an radiation inherently integrated circuit (IC) based on CMOS ...


Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2014

Current induced domain walls (DW) motion in magnetic nanowires or nano-stripes presents a novel approach to store and convey data. Combining with magnetic tunnel junction (MTJ) nanopillars, Racetrack memory (RM) becomes a new class of non-volatile memory thanks to its large storage capacity and fast data access. However, we need a relatively high current passing through the nanowire to move ...


Operation principle and design of a differential magnetic shape memory actuator

Fourtieth IAS Annual Meeting. Conference Record of the 2005 Industry Applications Conference, 2005., 2005

Magnetically controlled shape memory alloy (MSMA) exhibits large, reversible strains in the presence of a sufficiently high magnetic field, which provides a new way to produce motion and force. In this paper, the magnetic control properties of MSMA, the operation principle, design and control method of a differential MSMA actuator are introduced. In compare with the conventional MSMA actuator design, ...



Educational Resources on Magnetic Memory Designs

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IEEE.tv Videos

Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
HYUNSOO YANG - IEEE Magnetics Distinguished Lecture
Perpendicular magnetic anisotropy: From ultralow power spintronics to cancer therapy
Spin Dynamics in Inhomogeneously Magnetized Systems - Teruo Ono: IEEE Magnetics Society Distinguished Lecture 2016
Magnetic Nanowires: Revolutionizing Hard Drives, RAM, and Cancer Treatment
35 Years of Magnetic Heterostructures
High Frequency Magnetic Circuit Design for Power Electronics
Magnetic Materials and Magnetic Devices - Josep Fontcuberta: IEEE Magnetics Distinguished Lecture 2016
Magnetics + Mechanics + Nanoscale = Electromagnetics Future - Greg P. Carman: IEEE Magnetics Distinguished Lecture 2016
ASC-2014 SQUIDs 50th Anniversary: 2 of 6 - John Clarke - The Ubiquitous SQUID
IEEE Magnetics Distinguished Lecture - Mitsuteru Inoue
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
IMS 2012 Microapps - Electrical Thermal Coupled Solutions for Flip Chip Designs
A Comparison Between Single Purpose and Flexible Neuromorphic Processor Designs: IEEE Rebooting Computing 2017
A Discussion on Hard Drives
Micro-Apps 2013: How to Make Your Designs More Robust
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Magnetic Shield Implementation - EMC Society Demo
IEEE Magnetics 2014 Distinguished Lectures - JONATHAN COKER
Magmites: Wireless Resonant Magnetic Microrobots

IEEE-USA E-Books

  • Magnetoelectric Random Access Memory-Based Circuit Design by Using Voltage-Controlled Magnetic Anisotropy in Magnetic Tunnel Junctions

    We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory applications. We present and discuss specifically two applications, magnetoelectric random access memory (MeRAM) and ternary content-addressable memory (TCAM). The MEJ differs from a magnetic tunnel junction (MTJ) in that electric field is used to induce switching in lieu of substantial current flow in MTJ. Electric field control of magnetism can dramatically enhance the performance of magnetic memory devices in terms of switching energy efficiency and switching speed. The development of such an energy-efficient and ultrafast memory has a potential to change the paradigm of a hierarchical memory system in the conventional computer architecture. By combining speed, low power, and high density, electric-field-controlled magnetic memory merges features of multiple separate memory technologies used in today's memory hierarchy. The performance of a VCMA-MEJs-based MeRAM, especially in the case of one access transistor associated with one MEJ (1T-1R) structure, is evaluated by comparing it with that of phase-change RAM, resistive RAM, and spin transfer torque RAM. MeRAM can achieve ultrafast switching (&lt;;1 ns), low switching energy (~1 fJ), and compact cell size of 6 F<sup>2</sup> with a shared source region, as well as nonvolatility. For another application, we propose the VCMA-MEJ-based TCAM, which will be referred to as MeTCAM, consisting of 4T- 2MEJs. Since MeTCAM fully exploits the low power and high density features of the VCMA effect both in write and search operation modes, it obtains a fast searching speed (0.2 ns) with the smallest cell area (44 F<sup>2</sup>) compared to previous works.

  • Magnetic Random Accessible Memory Based Magnetic Content Addressable Memory Cell Design

    In this paper, we present a novel magnetic content addressable memory (MCAM) cell architecture. The proposed MCAM cell consists of four magnetic tunneling junction devices (MTJs). All previously proposed MCAM cell designs require both magnets of MTJ to be programmable. Such requirement poses a great challenge on device fabrication. This paper describe a new design based on conventional MTJs used in magnetic random accessible memory, i.e., only the top magnet is programmable while the bottom magnet is pinned. The feasibility of this design comes from the circuit connections based on the unique operation features of content addressable memory and the MTJs. The feasibility of the proposed operation has been demonstrated by numerical simulation.

  • Design of nonvolatile memory based on magnetic tunnel junction for special electronic systems

    Description of non-volatile memory based on magnetic tunnel junction is presented. A dynamic Verilog-A behavioral model and a Spice macro-model of the single memory cell is described. The advantages of the proposed models is demonstrated on a next generation revolutionary Magnetic Random Access Memory (MRAM) which we offer to implement on an radiation inherently integrated circuit (IC) based on CMOS technology.

  • Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires

    Current induced domain walls (DW) motion in magnetic nanowires or nano-stripes presents a novel approach to store and convey data. Combining with magnetic tunnel junction (MTJ) nanopillars, Racetrack memory (RM) becomes a new class of non-volatile memory thanks to its large storage capacity and fast data access. However, we need a relatively high current passing through the nanowire to move magnetic domain walls. This leads to a big challenge to design integration circuits and architecture for RM beyond the device level research. For instance, we find that the resistivity of nanowire material is a very critical parameter for the RM design. In this paper, we present the design of racetrack memory taking into account the physical prospects of magnetic domain wall motion in nanowires. By using an industrial CMOS 40 nm design kit and a perpendicular magnetic anisotropy (PMA) RM compact model, mixed SPICE simulations have been performed to analyze the area (e.g. 1 F2), speed and reliability performances.

  • Operation principle and design of a differential magnetic shape memory actuator

    Magnetically controlled shape memory alloy (MSMA) exhibits large, reversible strains in the presence of a sufficiently high magnetic field, which provides a new way to produce motion and force. In this paper, the magnetic control properties of MSMA, the operation principle, design and control method of a differential MSMA actuator are introduced. In compare with the conventional MSMA actuator design, the proposed differential MSMA actuator can compensate the temperature influence, reduce the excitation power and improve the accuracy of position control as well as the dynamic behavior. The validity and feasibility of the proposed structure and control strategy have been examined by the tested results of a prototype differential MSMA actuator.

  • Rate-Compatible Protograph LDPC Codes for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

    This paper proposes novel rate-compatible protograph LDPC (RCP-LDPC) codes to correct memory cell errors and mitigate the raw bit error rate (BER) diversity for spin-torque transfer magnetic random access memory (STT-MRAM). Since the STT-MRAM channel is asymmetric, we first apply an independent and identically distributed (i.i.d.) channel adapter to force the channel to be symmetric. We then propose to use the protograph extrinsic information transfer (PEXIT) algorithm, the asymptotic weight distribution (AWE) analysis, as well as the actual error rate performance as the combined guideline for designing protograph LDPC codes with short codeword lengths for STT-MRAM. By further applying a code extension approach, we construct novel RCP-LDPC codes that can work with a single encoder/decoder. Simulation results show that our proposed RCP-LDPC codes outperform the well-known rate-compatible AR4JA protograph codes.

  • Magnetic Content Addressable Memory

    In this paper, we propose a magnetic tunneling junction (MTJ)-based content addressable memory (CAM) design to simplify CAM bit from ten MOSFETs to one MTJ device. The MTJ CAM cell consists of a thin top electrode and vertical ring-shaped bottom electrode. The spin orientations in top and bottom electrodes can be programmed individually. The tunneling junction resistance represents the matching status between the data stored in top and bottom magnets. The top magnet is intentionally made thin so that it can be programmed with a low magnetic field without disturbing the thick bottom magnet. The bottom vertical ring-shaped magnet has programming-current enclosed inside the ring. The programming magnetic field is confined within the ring-shaped magnet. Our simulation based on Ansoft Maxwell (Pittsburgh, PA) software shows magnetic field confinement provides an order of magnitude difference between magnetic fields in the top and the bottom magnets separated by 2 nm. Landau-Liftshitz-Gilbert (LLG) micromagnetic simulations confirm that either magnet can be programmed without disturbing the other one

  • Application of change in permeability of magnetic shape memory (MSM) alloys for optimization of magnetic circuit in actuators

    Magnetic shape memory alloys, especially Ni-Mn-Ga alloys have been shown to have enormous potential to be used in electromagnetic (EM) actuators and sensors due to very long lifetime, fast response time, and large magnetic strain. They change their shape when subjected to external magnetic field. A number of physical phenomena accompanying the shape change also open up prospects for self-sensing or energy-harvesting applications. This paper concerns the use of changes in permeability of MSM alloys with strain to optimise actuator design. This is shown for a basic MSM actuator with very small air gap. Comparison of designs with and without “pre-strained” MSM element is presented based on field modelling results.

  • A Planar Magnetic Content Addressable Memory Cell

    In this paper, we present a novel magnetic content addressable memory (MCAM) cell design. The proposed MCAM cell consists of a magnetic tunneling junction (MTJ), where both magnets are programmable. The synthetic antiferromagnetic (SAF) structure is used for the top magnet of MTJ, which can be programmed in toggle mode by externally applied field. The bottom MTJ magnet is programmed by the magnetic fringe field from a programming line underneath the bottom magnet. The domain wall motion in the programming line is driven by the spin- polarized current. The feasibility of the proposed operation has been demonstrated by numerical micromagnetic simulation. The simulation results show a 2times margins on both top and bottom magnets programming field/current in the proposed planar MCAM cell design.

  • Robust High Speed Ternary Magnetic Content Addressable Memory

    Designing robust, low power, and delay ternary magnetic content addressable memory (TMCAM) using spintronic-based devices like magnetic tunnel junction (MTJ) is a challenge. Process variations in MTJ and transistor degrade the performance of ternary content-addressable memory (TCAM) as the number of bits increases. To bring TCAM using MTJ (TMCAM) to practical use for wide arrays (&gt;2048 bits), its cell has to be designed with large tolerance to all types of variations. Reducing the power consumption associated with searching without the increase in delay is also essential for the designing of TMCAMs. The proposed TMCAM cell has guaranteed read-disturbance immunity, low delay, and comparable power as compared with the reported MTJ-based magnetic-content- addressable memory (MCAM). Monte Carlo simulation was performed for proving the robustness of the proposed TMCAM by considering both variations in MTJ and transistor parameters. A Verilog-A model of the MTJ along with 45-nm CMOS technology is used for the simulation. A delay reduction of 1.23 times with power decrement of 1.23 times is obtained compared with previously reported MCAM for TMR = 3. This leads to a power-delay product improvement of 1.5 times for 2048-bit TMCAM.



Standards related to Magnetic Memory Designs

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IEEE Standard Microcomputer System Bus