What Is Rebooting Computing?

Rebooting computing is an IEEE-led initiative and research agenda that addresses the fundamental physical and architectural limits facing conventional silicon computing. For decades, progress in computer performance followed Moore's Law, the observation that transistor density on an integrated circuit doubles roughly every two years, and Dennard scaling, which held that power consumption per transistor fell as devices shrank. Both trends have stalled: transistors are approaching atomic dimensions, voltage scaling has halted, and power density has become a primary constraint. Rebooting computing asks what computer architectures, devices, and algorithms must look like when the classical scaling roadmap is no longer available.

The initiative spans semiconductor physics, computer architecture, algorithm design, and systems software. It does not prescribe a single successor technology but instead frames a set of open problems and invites the research community to pursue parallel paths toward energy-efficient, high-performance computation well beyond what conventional CMOS can deliver.

Energy Efficiency and Post-Moore Challenges

Energy per operation has become the dominant design metric in computing. Data center electricity consumption is a significant and growing fraction of global power use, and the energy cost of moving data between processor and memory frequently exceeds the cost of the arithmetic operation itself. The IEEE Rebooting Computing initiative catalogs the physical limits of silicon CMOS and frames the gap between current capabilities and the demands of emerging workloads such as large-scale machine learning and real-time sensor fusion.

Approximate computing, near-memory processing, and 3D chip stacking are near-term architectural responses that improve energy efficiency within the silicon paradigm. They reduce data movement, allow parallelism to be exploited locally, and trade small amounts of output accuracy for significant power savings in applications that are naturally tolerant of numerical imprecision.

Neuromorphic Computing

Neuromorphic computing draws on the architecture of biological neural circuits to build processors that perform pattern recognition and inference at energy levels orders of magnitude below those of conventional von Neumann machines. Neuromorphic chips implement spiking neural networks in silicon, using spike timing rather than precise analog or digital values to encode and transmit information. Intel's Loihi and IBM's TrueNorth are research prototypes that demonstrate low-power inference for sensory processing tasks. Research on neuromorphic systems explores both the hardware implementation and the learning algorithms needed to program spiking networks, including spike-timing-dependent plasticity and surrogate gradient methods.

Beyond-CMOS Architectures

Several device technologies are under investigation as long-term successors to or complements of CMOS transistors. Spintronic devices exploit the quantum mechanical spin of electrons rather than charge, offering the potential for non-volatile logic that retains state without power. Tunnel field-effect transistors (TFETs) use quantum tunneling to achieve sub-threshold swings below the 60 mV/decade thermal limit of conventional MOSFETs, enabling lower supply voltages. Carbon nanotube transistors and two-dimensional materials such as molybdenum disulfide offer high carrier mobility at reduced dimensions.

Quantum computing represents the most radical departure: quantum bits (qubits) exploit superposition and entanglement to tackle certain optimization and simulation problems that are intractable for classical computers. NIST's quantum information program develops the metrology and standards needed to characterize and benchmark quantum processors as the technology matures toward fault-tolerant operation.

Exascale and High-performance Computing

Exascale systems capable of 10^18 floating-point operations per second have been deployed at national laboratories, but sustaining that peak performance on real workloads requires co-designing applications, programming models, and hardware. Memory bandwidth and inter-node communication latency limit utilization on sparse and irregular computations. The rebooting computing agenda intersects with HPC through research on dataflow and spatial architectures, near-memory logic, and reconfigurable computing fabrics that can be tailored to the structure of scientific simulations.

Applications

• Accelerating deep learning inference at the edge with neuromorphic and analog processors
• Solving combinatorial optimization problems in logistics and drug discovery with quantum annealers
• Reducing data-center energy consumption through near-memory and processing-in-memory architectures
• Enabling real-time scientific data reduction at particle physics and radio astronomy facilities
• Building radiation-hard space computing with beyond-CMOS non-volatile logic
• Supporting autonomous vehicle perception with ultra-low-power spiking sensor fusion processors