What Is Cyclic Redundancy Check?

A cyclic redundancy check (CRC) is an error-detection scheme that appends a short fixed-length value, computed from a block of data, to that block before transmission or storage. The receiver recomputes the value over the received data and compares it to the appended field; a mismatch signals that the data has been corrupted. CRCs belong to the broader class of cyclic codes, which derive their mathematical structure from polynomial arithmetic over finite fields. They detect a wider range of error patterns than simple checksums while remaining inexpensive to compute in hardware, which has made them a standard component in data communications, file systems, and storage protocols for more than five decades.

Polynomial Division and CRC Computation

The mathematical foundation of a CRC is division in the ring of polynomials with coefficients in GF(2), the binary field. The data block is treated as the coefficients of a polynomial M(x), which is multiplied by x^r (a left shift by r bits) and then divided by a chosen generator polynomial G(x) of degree r. The remainder of this division, a polynomial of degree less than r, is the CRC value, also called the frame check sequence. The sender appends this remainder to the original message; the complete transmitted word is then exactly divisible by G(x) with a zero remainder. The receiver divides the received word by the same generator and checks for a zero remainder. The choice of generator polynomial determines which error patterns the CRC will and will not detect. CRC-32, defined by the generator polynomial used in IEEE 802.3 Ethernet and the ISO 3309 standard, detects all single-bit errors, all double-bit errors, all odd numbers of errors, all burst errors shorter than 33 bits, and most burst errors of 33 bits or longer in a message of up to 2^31 bits.

Error Detection Properties

The error-detection capability of a CRC depends on the degree and structure of the generator polynomial. A degree-r generator produces an r-bit CRC, and a well-chosen polynomial guarantees detection of all error bursts of length r or less. Burst errors, in which a contiguous run of bits is corrupted, are the dominant failure mode in many physical media because noise events tend to affect adjacent bits rather than isolated individual bits. CRC-16 (generator polynomial x^16 + x^15 + x^2 + 1, also called CRC-CCITT) is sufficient for most serial communication protocols; CRC-32 is standard for block storage and network frames where data blocks may be several kilobytes long. CRC-64 variants appear in some storage subsystems and cloud data integrity systems. CRCs do not correct errors and do not detect all possible error patterns; they are paired with retransmission protocols or forward error correction codes when correction is required.

Frame Check Sequences

A frame check sequence (FCS) is the specific field within a network frame or data link protocol data unit that carries the CRC value. In IEEE 802.3 Ethernet, the FCS occupies the final four bytes of every frame and carries a CRC-32 value computed over the destination address, source address, length, and payload fields. The IEEE 802 LAN/MAN Standards Committee specifies the generator polynomial, the initial seed, and the bit ordering for all Ethernet frame check sequences, ensuring interoperability across manufacturers. HDLC, USB, and the SATA storage interface similarly define FCS fields with specific CRC polynomials. The IETF RFC 3720 (iSCSI) specifies CRC-32C (using the Castagnoli polynomial) as the data digest for storage traffic over TCP/IP networks, selected for its superior error detection performance over the original CRC-32 at typical storage block sizes.

Applications

Cyclic redundancy check has applications in a wide range of disciplines, including:

• Computer networking: frame integrity verification in Ethernet, Wi-Fi (IEEE 802.11), and HDLC-based protocols
• Mass storage: sector-level integrity checking in hard disk drives, SSDs, and optical disc formats including CD, DVD, and Blu-ray
• Embedded systems: error detection in serial buses such as CAN, which mandates a 15-bit CRC on every frame for automotive and industrial use
• Compressed file formats: integrity verification in ZIP, gzip, and PNG files using CRC-32
• Telecommunications: burst error detection in SONET/SDH and ATM cell headers across carrier networks