Silicon

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Silicon is the most common metalloid. (Wikipedia.org)






Conferences related to Silicon

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2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.


2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAMs22. Phase Change Memory23. 3-Dimensional Memory24. MEMS Technology25. Thin Film Transistors26. Biosensors27. PV and Energy Harvesting28. Front End of Line (FEOL) R

  • 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

    Silicon IC, Silicon/germanium devices , Interconnect , Low K and High Kdielectric , Advance Memories , nano -electronics, Organic and Compound semiconductor devices ,sensors and MEMS, Semiconductor material erization, Reliability , Modeling and simulation,Packaging and testing , Digital, Analog, Mixed Signal IC and SOC design technology,Low -power, RF devices & circuits, ICCAD

  • 2010 IEEE 10th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

    Silicon IC, Silicon/germanium devices , Interconnect , Low K and High K dielectric , Advance Memories , nano-electronics, Organic and Compound semiconductor devices , sensors and MEMS, Semiconductor material characterization, Reliability , Modeling and simulation, Packaging and testing , Digital, Analog, Mixed Signal IC and SOC design technology,Low-power, RF devices & circuits, IC CAD .


2014 IEEE 40th Photovoltaic Specialists Conference (PVSC)

The PVSC is a technical conference dedicated to the science and application of photovoltaics for solar electricity generation. Technical Program Areas: 1. Fundamentals and New Concepts for Future Technologies 2. Thin Film Polycrystalline Photovoltaics 3. III-V and Concentrator Technologies 4. Crystalline Silicon Technologies 5. Thin Film Silicon Based PV Technologies 6. Organic Photovoltaics 7. Space Technologies 8. Characterization and Measurement Methods 9. PV Modules and Manufacturing 10. PV Systems and Applications 11. PV Velocity Forum


2014 IEEE 45th Semiconductor Interface Specialists Conference (SISC)

The SISC provides a unique forum for device engineers, solid-state physicists, and materials scientists to discuss issues of common interest. Principal topics for discussion at SISC are semiconductor/insulator interfaces, the physics of insulating thin films, and the interaction among materials science, device physics, and state-of-the-art technology.


2013 14th International Conference on Ultimate Integration on Silicon (ULIS)

The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2012 13th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2011 12th International Conference on Ultimate Integration on Silicon (ULIS)

    ULIS is an annual conference that regroups the European research community working on advanced silicon devices and nanodevices. It has been held annually since 2000. The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2009 10th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2008 9th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices for switches, memory and novel applications such as sensors and bioelectronics.


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Periodicals related to Silicon

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Lightwave Technology, Journal of

All aspects of optical guided-wave science, technology, and engineering in the areas of fiber and cable technologies; active and passive guided-wave componentry (light sources, detectors, repeaters, switches, fiber sensors, etc.); integrated optics and optoelectronics; systems and subsystems; new applications; and unique field trials.


Selected Topics in Quantum Electronics, IEEE Journal of

40% devoted to special issues published in J. Quantum Electronics. Other topics: solid-state lasers, fiber lasers, optical diagnostics for semi-conductor manufacturing, and ultraviolet lasers and applications.


Semiconductor Manufacturing, IEEE Transactions on

Addresses innovations of interest to the integrated circuit manufacturing researcher and professional. Includes advanced process control, equipment modeling and control, yield analysis and optimization, defect control, and manufacturability improvement. It also addresses factory modelling and simulation, production planning and scheduling, as well as environmental issues in semiconductor manufacturing.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...




Xplore Articles related to Silicon

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A high sensitive piezoresistive sensor for stress measurements in packaged semiconductor die

A. Mian; J. C. Suhling; R. C. Jaeger 2006 IEEE Workshop on Microelectronics and Electron Devices, 2006. WMED '06., 2006

The authors have developed new two-dimensional piezoresistive stress sensors that replace conventional serpentine resistor rosettes. These sensors are named van der Pauw (VDP) sensors as they are based upon four-terminal van der Pauw type resistance measurements. The resistance of such a sensor is size independent, and hence can be made as small as lithographically possible to capture stresses in critical ...


Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

R. Tsuchiya; M. Horiuchi; S. Kimura; M. Yamaoka; T. Kawahara; S. Maegawa; T. Ipposhi; Y. Ohji; H. Matsuoka IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004

We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal ...


Ideal Time–Frequency Masking Algorithms Lead to Different Speech Intelligibility and Quality in Normal-Hearing and Cochlear Implant Listeners

Raphael Koning; Nilesh Madhu; Jan Wouters IEEE Transactions on Biomedical Engineering, 2015

Hearing impaired listeners using cochlear implants (CIs) suffer from a decrease in speech intelligibility (SI) in adverse listening conditions. Time- frequency masks are often applied to perform noise suppression in an attempt to increase SI. Two important masks are the so-called ideal binary mask (IBM) with its binary weights and the ideal Wiener filter (IWF) with its continuous weights. It ...


Optical absorption enhancement in solar cell employing plasmonic nanowire as the core of C-Si nanowire

Md. Ibrahim Khalil; Atiqur Rahman; Arshad M Chowdhury; Gee-Kung Chang CLEO: 2013, 2013

We propose a simple plasmonic nanostructure based nanowire crystalline Silicon solar cell by integrating silver core with nanowire. We found 63% better ultimate efficiency compared to conventional nanowire structures for fixedfilling ratio and length.


A scientific approach in wind energy courses for electrical engineers

M. J. Duran; F. Barrero; I. González-Prieto; H. Guzman; A. Pozo; M. Bermudez; C. Martin 2016 Technologies Applied to Electronics Teaching (TAEE), 2016

Teaching and research are joint activities at University level, but in many cases it is found that both activities have a poor connection. While the scientific method based on well-known steps is commonly applied at research level, this methodology and the associated know-how are rarely integrated in degree courses. This work describes the integration of theory, simulation, lab-scale experiments and ...


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Educational Resources on Silicon

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eLearning

A high sensitive piezoresistive sensor for stress measurements in packaged semiconductor die

A. Mian; J. C. Suhling; R. C. Jaeger 2006 IEEE Workshop on Microelectronics and Electron Devices, 2006. WMED '06., 2006

The authors have developed new two-dimensional piezoresistive stress sensors that replace conventional serpentine resistor rosettes. These sensors are named van der Pauw (VDP) sensors as they are based upon four-terminal van der Pauw type resistance measurements. The resistance of such a sensor is size independent, and hence can be made as small as lithographically possible to capture stresses in critical ...


Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

R. Tsuchiya; M. Horiuchi; S. Kimura; M. Yamaoka; T. Kawahara; S. Maegawa; T. Ipposhi; Y. Ohji; H. Matsuoka IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004

We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal ...


Ideal Time–Frequency Masking Algorithms Lead to Different Speech Intelligibility and Quality in Normal-Hearing and Cochlear Implant Listeners

Raphael Koning; Nilesh Madhu; Jan Wouters IEEE Transactions on Biomedical Engineering, 2015

Hearing impaired listeners using cochlear implants (CIs) suffer from a decrease in speech intelligibility (SI) in adverse listening conditions. Time- frequency masks are often applied to perform noise suppression in an attempt to increase SI. Two important masks are the so-called ideal binary mask (IBM) with its binary weights and the ideal Wiener filter (IWF) with its continuous weights. It ...


Optical absorption enhancement in solar cell employing plasmonic nanowire as the core of C-Si nanowire

Md. Ibrahim Khalil; Atiqur Rahman; Arshad M Chowdhury; Gee-Kung Chang CLEO: 2013, 2013

We propose a simple plasmonic nanostructure based nanowire crystalline Silicon solar cell by integrating silver core with nanowire. We found 63% better ultimate efficiency compared to conventional nanowire structures for fixedfilling ratio and length.


A scientific approach in wind energy courses for electrical engineers

M. J. Duran; F. Barrero; I. González-Prieto; H. Guzman; A. Pozo; M. Bermudez; C. Martin 2016 Technologies Applied to Electronics Teaching (TAEE), 2016

Teaching and research are joint activities at University level, but in many cases it is found that both activities have a poor connection. While the scientific method based on well-known steps is commonly applied at research level, this methodology and the associated know-how are rarely integrated in degree courses. This work describes the integration of theory, simulation, lab-scale experiments and ...


More eLearning Resources

IEEE-USA E-Books

  • Nanotechnology from a Micromachinist's Point of View

    This chapter contains sections titled: Scale of Micromachined Devices, Evolution of Micromachining, Engineering with Silicon, Micromachining Technology, Micromachined Pressure Sensors, Other Applications of Micromachining, Micromachining Complex Machines, Micromachining and Nanotechnology, Notes, Discussion

  • Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology

    A 100 nm gate silicon???on???insulator complementary metal oxide semiconductor (SOI CMOS) has been successfully produced using high???quality separation by implanted oxygen (SIMOX) substrates and an advanced design concept for the subquarter micron regime based on a simple device model. In addition, a 85 nm gate SOI nMOSFET and an SOI pMOSFET with 8 nm thick silicon active layers has been produced. Device performance of the 100 nm gate SOI CMOS reveals that it is a promising device for future SOI CMOS ICs.The high parasitic resistance of the source and drain regions of the 100 nm gate SOI CMOS tends to increase the propagation delay time. However, by reducing the parasitic resistance we can expect 100 nm gate SOI CMOS devices with delay time of the order of 10 ps. The prospects for improving the performance of 100 nm gate SOI CMOS devices are discussed in detail.

  • The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's

    The results of a comprehensive investigation into the characteristics and optimization of Inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extncts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in melallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model aecuncy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technolocies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

  • The People

    Silicon Valley, a small place with few identifiable geologic or geographic features, has achieved a mythical reputation in a very short time. The modern material culture of the Valley may be driven by technology, but it also encompasses architecture, transportation, food, clothing, entertainment, intercultural exchanges, and rituals.Combining a reporter's instinct for a good interview with traditional archaeological training, Christine Finn brings the perspectives of the past and the future to the story of Silicon Valley's present material culture. She traveled the area in 2000, a period when people's fortunes could change overnight. She describes a computer's rapid trajectory from useful tool to machine to be junked to collector's item. She explores the sense that whatever one has is instantly superseded by the next new thing -- and the effect this has on economic and social values. She tells stories from a place where fruit-pickers now recycle silicon chips and where more money can be made babysitting for post-IPO couples than working in a factory. The ways that people are working and adapting, are becoming wealthy or barely getting by, are visible in the cultural landscape of the fifteen cities that make up the area called "Silicon Valley."

  • Silicon and Gallium Arsenide in High Temperature Electronics Applications

    Electronic circuits and systems which can operate at temperatures up to 250°C or even higher become more and more important. It can be shown that Si as semiconductor material can be used up to this temperature provided that circuit structures are optimized to handle the parasitic effects rising with temperature. For even higher temperatures up to 350°C GaAs can be used. Other problems going along with high temperature applications arise from material characteristics as melting point, mechanical stability, insulating characteristics and migration problems. This paper reports on a German Joint Research project dealing with the problems mentioned above. Some of them could be solved satisfactory, some problems are still existing.

  • Semiconductor Diode Lasers

    This chapter contains sections titled: Basics of Semiconductor Diode Lasers Semiconductor Basics Light Emission at Junctions Layers and Confinement in Diode Lasers Confinement in the Junction Plane Edge-Emitting Diode Lasers Surface-Emitting Diode Lasers Quantum Wells and Dots Quantum Cascade Lasers Optical Properties of Diode Lasers Diode Laser Materials and Wavelengths Silicon Lasers Packaging and Specialization of Diode Lasers What Have We Learned?

  • Experimental Consideration for Modeling of Lubistor Operation

    An experimental characterization of Lubistors has been carried out through the employment of SIMOX technology and the following results were obtained: (i) An oxygen-doped silicon (ODS) layer should be placed between the upper silicon layer and buried oxide layer to achieve the original Lubistor characteristic; that is, anode-to-cathode current is cut off by enhancement-mode gate bias.(ii) In the Lubistor's ON state, a large potential drop exists only near a high-low junction terminal, which must be supported by the depletion layer. (iii) In the Lubistor's OFF state, a large potential drop exists near a pn- junction terminal, which must also be supported by the depletion layer. A simplified analysis is carried out to clarify the Lubistor's operation mechanism. A theoretical model is used to qualitatively support experimental results.

  • Daniel Bricklin

    Who are the masterminds of today's electronic revolution and what motivated them? That's the question Time correspondent Robert Slater asked as he traveled to Silicon Valley to interview the designers, entrepreneurs, hardware engineers, and software writers who have given us the modern computer.Robert Slater is a member of the reporting staff of the Time Jerusalem bureau.

  • Three-Dimensional Nand Flash Cell

    This chapter introduces major three-dimensional (3D) cells. The bit cost scalable (BiCS) cell has a new structure of the stacked control gate layers and vertical poly-silicon channel. The thinner poly-silicon channel can obtain the easier electrostatic control performed by the gate electrode over the thinner body and the smaller poly-silicon grains which reduce the impact on the channel current of statistical variation of smaller grain size configuration. Terabit cell array transistor (TCAT) has a similar structure of BiCS, with a vertical poly-silicon channel, stacked word lines, and a silicon nitride (SiN) charge storage layer of the surrounding gate SONOS cell. The chapter describes a process sequence of vertical gate NAND (VG-NAND) cell and proposes a dual control gate with a surrounding floating-gate (DC-SF) cell for 3D NAND flash memory. This structure allows to apply floating gate to a 3D stacked cell structure with minimal cell size and high coupling ratio.

  • Front Matter

    This chapter contains sections titled: Half Title, Title, Copyright, Contents, Preface, Acknowledgments



Standards related to Silicon

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No standards are currently tagged "Silicon"