Silicon

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Silicon is the most common metalloid. (Wikipedia.org)






Conferences related to Silicon

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM//IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.


2020 IEEE 16th International Workshop on Advanced Motion Control (AMC)

AMC2020 is the 16th in a series of biennial international workshops on Advanced Motion Control which aims to bring together researchers from both academia and industry and to promote omnipresent motion control technologies and applications.


2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies


2019 IEEE 46th Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2019 IEEE Applied Power Electronics Conference and Exposition (APEC)

APEC focuses on the practical and applied aspects of the power electronics business. The conference addresses issues of immediate and long term importance to practicing power electronics engineer.


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Periodicals related to Silicon

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


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Xplore Articles related to Silicon

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Preparation of novel SiGe-free strained Si on insulator substrates

[{u'author_order': 1, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37282532200', u'full_name': u'Langdo', u'id': 37282532200}, {u'author_order': 2, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37282744800', u'full_name': u'Lochtefeld', u'id': 37282744800}, {u'author_order': 3, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275469400', u'full_name': u'Currie', u'id': 37275469400}, {u'author_order': 4, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/38185233500', u'full_name': u'Hammond', u'id': 38185233500}, {u'author_order': 5, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37266327700', u'full_name': u'Yang', u'id': 37266327700}, {u'author_order': 6, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37272552500', u'full_name': u'Carlin', u'id': 37272552500}, {u'author_order': 7, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37326260400', u'full_name': u'Vineis', u'id': 37326260400}, {u'author_order': 8, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37282535500', u'full_name': u'Braithwaite', u'id': 37282535500}, {u'author_order': 9, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37282745100', u'full_name': u'Badawi', u'id': 37282745100}, {u'author_order': 10, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37282745500', u'full_name': u'Bulsara', u'id': 37282745500}, {u'author_order': 11, u'affiliation': u'AmberWave Syst. Corp., Salem, NH, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275062700', u'full_name': u'Fitzgerald', u'id': 37275062700}] 2002 IEEE International SOI Conference, 2002

A novel SiGe-free SSOI substrate technology has been described. This method enables the fabrication of well controlled, epitaxially-defined, thin strained Si layers directly on insulator layers. Tensile strain levels of greater than 1% have been demonstrated in these structures, and are not diminished after thermal anneal cycles. The strain-inducing relaxed SiGe layer is absent from the final structure, eliminating some ...


CMOS devices strained-silicon technology

[{u'author_order': 1, u'full_name': u'Yee-Chia Yeo'}, {u'author_order': 2, u'full_name': u'H.C.-H. Wang'}] IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005

None


Enhancing CMOS Transistor Performance Using Lattice-Mismatched Materials in Source/Drain Regions

[{u'author_order': 1, u'affiliation': u'Department of Electrical and Computer Engineering, National University of Singapore, 117576, Singapore. Phone: +65 6516-2298, Fax: +65 6779 1103, Email: yeo@ieee.org', u'authorUrl': u'https://ieeexplore.ieee.org/author/37272715000', u'full_name': u'Yee-Chia Yeo', u'id': 37272715000}] 2006 International SiGe Technology and Device Meeting, 2006

Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling


CMOS Devices - Strained Silicon

[] 2006 International Electron Devices Meeting, 2006

None


Ion-beam hydrogenation of sputter-deposited amorphous silicon and amorphous silicon-germanium alloys

[{u'author_order': 1, u'affiliation': u'Colorado Sch. of Mines, Golden, CO, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37343304700', u'full_name': u'X.J. Deng', u'id': 37343304700}, {u'author_order': 2, u'authorUrl': u'https://ieeexplore.ieee.org/author/37349060400', u'full_name': u'Y.S. Tsuo', u'id': 37349060400}, {u'author_order': 3, u'authorUrl': u'https://ieeexplore.ieee.org/author/37344270800', u'full_name': u'J.U. Trefny', u'id': 37344270800}] IEEE Conference on Photovoltaic Specialists, 1990

The posthydrogenation of undoped and boron-doped amorphous silicon and amorphous silicon-germanium alloys was studied using a Kaufman ion-beam source. These materials were deposited in a two-source radio frequency (RF) excited argon plasma sputter-deposition system. After ion-beam posthydrogenation, the optical bandgap of amorphous silicon-germanium alloys increased from about 1.12 eV to 1.47 eV, and the material has an air mass one ...


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Educational Resources on Silicon

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eLearning

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IEEE-USA E-Books

  • Supplementary Study on Buried Oxide Characterization:

    This chapter proposes a macroscopic physical model for the buried oxide having a transition layer in a SIMOX substrate to estimate the parasitic capacitance. The Clausius-Mossotti relationship for two media is introduced into the model, employing an empirical factor to match with a high-frequency response. Peaks in the capacitance dependence on frequency appear only in devices with the buried oxide having a transition layer. This property can be explained by the proposed model. It is also shown that the transition layer adjacent to buried oxide should be eliminated to reduce parasitic capacitance. [©1992 IEEE. Reprinted, with permission, from Y. Omura and K. Izumi, A macroscopic physical model and capacitive response of the buried oxide having a transition layer in a SIMOX substrate,_IEEE Transactions on Electron Devices_, vol. 39, pp. 1916-1921, 1992.]

  • Experimental Consideration for Modeling of Lubistor Operation

    An experimental characterization of Lubistors has been carried out through the employment of SIMOX technology and the following results were obtained: (i) An oxygen-doped silicon (ODS) layer should be placed between the upper silicon layer and buried oxide layer to achieve the original Lubistor characteristic; that is, anode-to-cathode current is cut off by enhancement-mode gate bias.(ii) In the Lubistor's_ON_state, a large potential drop exists only near a high-low junction terminal, which must be supported by the depletion layer. (iii) In the Lubistor's_OFF_state, a large potential drop exists near a pn- junction terminal, which must also be supported by the depletion layer. A simplified analysis is carried out to clarify the Lubistor's operation mechanism. A theoretical model is used to qualitatively support experimental results.

  • Negative Conductance Properties in Extremely Thin SOI Lubistors

    In this chapter the occurrence of negative conductance at temperatures of less than 90 K in an SOI Lubistor with a 10-nm-thick silicon layer fabricated on a SIMOX substrate is reported. Through comparison with the performance of an SOI Lubistor with a 90-nm-thick silicon layer, the advantages of the two- dimensional confinement effect are shown. [Copyright 1996. The Japan Society of Applied Physics. Y. Omura, Negative conductance properties in extremely thin silicon-on-insulator (SOI) insulated-gate pn-junction devices (SOI surface tunnel transistors),_Japanese Journal of Applied Physics_, vol. 35, pp. L1401-L1403, 1996.]

  • Modern Applications of the pn Junction

    This chapter reviews various applications of the pn junction from the viewpoint of a future extention of applications.

  • Possible Implementation of SOI Lubistors into Conventional Logic Circuits

    Possible application of the SOI Lubistor to logic circuits is reviewed. TFET- based logic and conventional CMOS logic configuration are introduced.

  • Supplementary Consideration of Characteristics of Forward-Biased Ultra-Thin Lubistors

    In this chapter, the low-temperature behavior of forward-biased Lubistors fabricated with a 10-nm-thick silicon-on-insulator (SOI) layer is described. At low temperature, a step-like current oscillation is observed that depends on gate voltage. It is also demonstrated that the effective activation energies of generation-recombination centers are shallower than expected from the theoretical calculations in Chapter 12.

  • Planar Onboard EBG Filters for Common Mode Current Reduction

    This chapter reviews the role of common mode (CM) filters in high‐density printed circuit board (PCB) designs and the previously analyzed beneficial properties of the electromagnetic bandgap (EBG) structures. It introduces the concept of a CM filter based on patch resonant cavities and the operating principle underlying the construction of EBG‐based CM filters. The main goal of the chapter is to introduce the design approach that has to be used in the building of EBG‐based CM filters, and in particular the attention is focused on the so‐called onboard filters. The chapter describes different design strategies and states proper considerations in order to target the EBG filter to specific design purposes, such as the improvement of the filter attenuation and bandwidth, or to minimize the occupied surface. Finally, it describes the main advantages and disadvantages of the considered structures so that the optimum design solution can be implemented.

  • EM Topology for Interference Control

    Interference control for large systems is complicated because of the physical and electrical complexity of the systems. This chapter discusses electromagnetic topology and its relation to interference control. It covers the various aspects involved in partitioning of systems by nested enclosures and topological concepts to preserve shielding integrity. The chapter introduces the concept of nested enclosures, and shows the proper techniques of passing grounds and other conductors through the shield. It also discusses the effects of apertures on shielding effectiveness and shows how shielding effectiveness can be degraded by fields diffusing through conductive surfaces. Apertures are usually required for access such as windows and doors, ventilation, and a host of other facility requirements. These apertures must be designed so that access is provided without compromising the electromagnetic compatibility of the system. The chapter includes a design example to calculate the voltage induced in a metallic loop placed on a spherical shield of different metals.

  • Noise Characteristics and Modeling of Lubistor

    This chapter describes the noise characteristics of various SOI Lubistors with anode-offset regions. The static characteristics of these devices are modeled for the noise analysis; the model is composed of a series of a MOSFET and the pn junction. It is shown experimentally that the noise power of the devices is proportional to_I__A__n_(_n_> 0), where_I__A_is the anode current. Since the noise characteristics are not explained by conventional theory, a new model based of a phenomenological consideration is proposed. It is shown that the proposed basic model, which is compatible with the conventional Hooge model, can explain the experimental results. The influence of the anode-offset length is also discussed and modeled. [Reprinted with permission from S. Wakita and Y. Omura,_Journal of Applied Physics_, vol. 91, p. 2143, 2002. Copyright 2002, American Institute of Physics.]

  • Replication Techniques for Digital Optics

    This chapter contains sections titled:The LIGA ProcessMold Generation TechniquesEmbossing TechniquesThe UV Casting ProcessInjection Molding TechniquesThe Sol‐Gel ProcessThe Nano‐replication ProcessA Summary of Replication Technologies



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