Conferences related to SDRAM

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2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.


2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAMs22. Phase Change Memory23. 3-Dimensional Memory24. MEMS Technology25. Thin Film Transistors26. Biosensors27. PV and Energy Harvesting28. Front End of Line (FEOL) R


2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world

  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS)

    The Symposium will focus on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability. The ISCAS 2010 will include oral and poster sessions; tutorials given by experts in state-of-the-art topics; and special sessions, with the aim of complementing the regular program with topics of particular interest to the community that cut across and beyond disciplines traditionally represented at ISCAS.

  • 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012

    2012 International Symposium on Circuits and Systems (ISCAS 2012) aims at providing the world's premier forum of leading researchers in circuits and systems areas from academia and industries, especially focusing on Convergence of BINET (BioInfoNanoEnviro Tech.) which represents IT, NT and ET and leading Human Life Revolutions. Prospective authors are invited to submit papers of their original works emphasizing contributions beyond the present state of the art. We also welcome proposals on special tuto

  • 2011 IEEE International Symposium on Circuits and Systems (ISCAS)

    The IEEE International Symposium on Circuits and Systems (ISCAS) is the world's premier networking forum of leading researchers in the highly active fields of theory, design and implementation of circuits and systems.

  • 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010

    ISCAS is a unique conference dealing with circuits and systems. It's the yearly "rendez-vous" of leading researchers, coming both from academia and industry, in the highly active fields of theory, design and implementation of circuits and systems. The Symposium will focus on circuits and systems for high quality life and consumer technologies, including mobile communications, advanced multimedia systems, sensor networks and Nano-Bio Circuit Fabrics and Systems.

  • 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

    Analog Signal Processing, Biomedical Circuits and Systems, Blind Signal Processing, Cellular Neural Networks and Array Computing, Circuits and Systems for Communications, Computer-Aided Network Design, Digital Signal Processing, Life-Science Systems and Applications, Multimedia Systems and Applications, Nanoelectronics and Gigascale Systems, Neural Systems and Applications, Nonlinear Circuits and Applications, Power Systems and Power Electronic Circuits, Sensory Systems, Visual Signal Processing and Communi

  • 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008


2013 IEEE 10th International Conference on ASIC (ASICON 2013)

I. Design Techniques[1] VLSI Design and Circuits[2] Analog, Mixed Signal and RF Circuits[3] Application-Specific SoCs[4] Circuits and Systems for Wireless Communications [5] Testing, Reliability, Fault-Tolerance[6] Advanced MemoryII. CAD Techniques[7] Circuits Simulation, Synthesis, Verification and Physical design[8] CAD for system, Design for Manufacturing and TestingIII. New Techniques, new processing, new devices and their applications[9] MEMS Techniques[10] Nanoelectronics and Gigascale systems[11] New Devices: Hetrojunction Devices, Fin FET, CNT MTJ Devices,, 3-D integration, etc..[12] Advanced Interconnection Technology, High K/Metal gate technology and other VLSL New Processing, New technologies .[13] VLSI application for Energy generation, conservation and control,IC Design, Analog Circuit, Mixed Signal & RF Circuits, SOC, Wireless Communication, IC Testing, Reliebility, CAD Techniques, Synthesis, Verification, Physical Design, DMF, Memory, MEMS, 3D IC, High K/


2013 IEEE 11th International Conference on Electronic Measurement & Instruments (ICEMI)

ICEMI is invited authors to submit original papers in any but not limited as following areas: Science Foundation of Instrument and Measurement Innovative Designing of Instrument and Test System Applications on Instrument and Testing Signal & Image Processing Sensor and Non-electric Measurement Communication and Network Test Systems Control Theory and Application Condition Monitoring, Fault Diagnosis and Prediction Other Relevant Theories and Technologies


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Periodicals related to SDRAM

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Broadcasting, IEEE Transactions on

Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


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Most published Xplore authors for SDRAM

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Xplore Articles related to SDRAM

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Optimal Data Mapping for Motion Compensation in H.264 Video Decoding

[{u'author_order': 1, u'affiliation': u'Dep. Electronics Engineering, National Chiao-Tung University, 1001 Ta-Hsueh Rd., Hsinchu, Taiwan, e-mail: isis@twins.ee.nctu.edu.tw', u'full_name': u'Guo-Shiuan Yu'}, {u'author_order': 2, u'affiliation': u'Dep. Electronics Engineering, National Chiao-Tung University, 1001 Ta-Hsueh Rd., Hsinchu, Taiwan, e-mail: tschang@twins.ee.nctu.edu.tw', u'full_name': u'Tian Sheuan Chang'}] 2007 IEEE Workshop on Signal Processing Systems, None

Long initial access cycles of SDRAM are the major performance burden of motion compensation in a video decoder. To minimize its effect while improve overall available memory bandwidth, this paper presents an optimal data mapping scheme for motion compensation in H.264 video coding. This scheme allocates the video data into suitable address and bank according to the access characteristics of ...


Improved Power Modeling of DDR SDRAMs

[{u'author_order': 1, u'affiliation': u'Comput. Eng., Tech. Univ. Delft, Delft, Netherlands', u'full_name': u'Karthik Chandrasekar'}, {u'author_order': 2, u'affiliation': u'Electron. Syst., Tech. Univ. Eindhoven, Eindhoven, Netherlands', u'full_name': u'Benny Akesson'}, {u'author_order': 3, u'affiliation': u'Electron. Syst., Tech. Univ. Eindhoven, Eindhoven, Netherlands', u'full_name': u'Kees Goossens'}] 2011 14th Euromicro Conference on Digital System Design, None

Power modeling and estimation has become one of the most defining aspects in designing modern embedded systems. In this context, DDR SDRAM memories contribute significantly to system power consumption, but lack accurate and generic power models. The most popular SDRAM power model provided by Micron, is found to be inaccurate or insufficient for several reasons. First, it does not consider ...


Model-guided strip size selection for minimal execution time on imagine stream processor

[{u'author_order': 1, u'affiliation': u'PDL, School of Computer, National University of Defense Technology, 410073, China', u'full_name': u'Jing Du'}, {u'author_order': 2, u'affiliation': u'PDL, School of Computer, National University of Defense Technology, 410073, China', u'full_name': u'Yuhua Tang'}, {u'author_order': 3, u'affiliation': u'PDL, School of Computer, National University of Defense Technology, 410073, China', u'full_name': u'Fujiang Ao'}, {u'author_order': 4, u'affiliation': u'PDL, School of Computer, National University of Defense Technology, 410073, China', u'full_name': u'Tao Tang'}, {u'author_order': 5, u'affiliation': u'PDL, School of Computer, National University of Defense Technology, 410073, China', u'full_name': u'Xuejun Yang'}] 2008 8th IEEE International Conference on Computer and Information Technology, None

Strip-mining is a critical optimization for improving the effectiveness of memory hierarchy of Imagine. In this paper, we present an efficient compiler algorithm for selecting the optimal strip size to minimize the execution time of stream programs. First, we build a graceful analytical model that characterizes the effect of strip size on key performance factors. Then, we design a novel ...


An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

[{u'author_order': 1, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Seung-Jun Bae'}, {u'author_order': 2, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Kwang-Il Park'}, {u'author_order': 3, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Jeong-Don Ihm'}, {u'author_order': 4, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Ho-Young Song'}, {u'author_order': 5, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Woo-Jin Lee'}, {u'author_order': 6, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Hyun-Jin Kim'}, {u'author_order': 7, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Kyoung-Ho Kim'}, {u'author_order': 8, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Yoon-Sik Park'}, {u'author_order': 9, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Min-Sang Park'}, {u'author_order': 10, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Hong-Kyong Lee'}, {u'author_order': 11, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Sam-Young Bang'}, {u'author_order': 12, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Gil-Shin Moon'}, {u'author_order': 13, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Seok-Won Hwang'}, {u'author_order': 14, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Young-Chul Cho'}, {u'author_order': 15, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Sang-Jun Hwang'}, {u'author_order': 16, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Dae-Hyun Kim'}, {u'author_order': 17, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Ji-Hoon Lim'}, {u'author_order': 18, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Jae-Sung Kim'}, {u'author_order': 19, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Sung-Hoon Kim'}, {u'author_order': 20, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Seong-Jin Jang'}, {u'author_order': 21, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Joo Sun Choi'}, {u'author_order': 22, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Young-Hyun Jun'}, {u'author_order': 23, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Kinam Kim'}, {u'author_order': 24, u'affiliation': u'Samsung Electron., Gyeonggu-Do', u'full_name': u'Soo-In Cho'}] IEEE Journal of Solid-State Circuits, 2008

4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single ...


An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

[{u'author_order': 1, u'affiliation': u'Samsung Electron., Hwasung', u'full_name': u'Kyu-hyoun Kim'}, {u'author_order': 2, u'full_name': u'Uksong Kang'}, {u'author_order': 3, u'full_name': u'Hoe-Ju Chung'}, {u'author_order': 4, u'full_name': u'Duk-Ha Park'}, {u'author_order': 5, u'full_name': u'Woo-Seop Kim'}, {u'author_order': 6, u'full_name': u'Young-Chan Jang'}, {u'author_order': 7, u'full_name': u'Moonsook Park'}, {u'author_order': 8, u'full_name': u'Hoon Lee'}, {u'author_order': 9, u'full_name': u'Jin-Young Kim'}, {u'author_order': 10, u'full_name': u'Jung Sunwoo'}, {u'author_order': 11, u'full_name': u'Hwan-Wook Park'}, {u'author_order': 12, u'full_name': u'Hyun-Kyung Kim'}, {u'author_order': 13, u'full_name': u'Su-Jin Chung'}, {u'author_order': 14, u'full_name': u'Jae-Kwan Kim'}, {u'author_order': 15, u'full_name': u'Hyung-Seuk Kim'}, {u'author_order': 16, u'full_name': u'Kee-Won Kwon'}, {u'author_order': 17, u'full_name': u'Young-Taek Lee'}, {u'author_order': 18, u'full_name': u'Joo Sun Choi'}, {u'author_order': 19, u'full_name': u'Changhyun Kim'}] 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, None

A 288Mb deca-data rate SDRAM with an I/O error-detection scheme is developed. Deca-data rate is proposed to include CRC for the higher data-rate beyond 5Gb/s/pin using a conventional DRAM process. Several techniques, including an area-efficient cell array consisting oftwo6F2 cells are adopted to enhance the core cycle speed. Measurement results show that the chip has a peak read or write ...


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Educational Resources on SDRAM

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IEEE-USA E-Books

  • Content‐and Entertainment‐Centric Software

    iCLouds and MyClouds, Resolution expectations, Resolution, displays and the human visual system, Frame rate expectations, Memory expectations over time, Memory options, Gaming in the Cloud and Gaming and TV integration, Solid state storage, Flash (Nor and Nand), SRAM and SDRAM, The SIM Card, Compact Flash, Smart Media, Multi Media Cards, Memory Stick, SD (Secure Digital) Cards, xD Picture Cards, USB Flash Drives/Portable hard drives



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