Conferences related to SDRAM

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.


2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAMs22. Phase Change Memory23. 3-Dimensional Memory24. MEMS Technology25. Thin Film Transistors26. Biosensors27. PV and Energy Harvesting28. Front End of Line (FEOL) R


2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world

  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS)

    The Symposium will focus on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability. The ISCAS 2010 will include oral and poster sessions; tutorials given by experts in state-of-the-art topics; and special sessions, with the aim of complementing the regular program with topics of particular interest to the community that cut across and beyond disciplines traditionally represented at ISCAS.

  • 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012

    2012 International Symposium on Circuits and Systems (ISCAS 2012) aims at providing the world's premier forum of leading researchers in circuits and systems areas from academia and industries, especially focusing on Convergence of BINET (BioInfoNanoEnviro Tech.) which represents IT, NT and ET and leading Human Life Revolutions. Prospective authors are invited to submit papers of their original works emphasizing contributions beyond the present state of the art. We also welcome proposals on special tuto

  • 2011 IEEE International Symposium on Circuits and Systems (ISCAS)

    The IEEE International Symposium on Circuits and Systems (ISCAS) is the world's premier networking forum of leading researchers in the highly active fields of theory, design and implementation of circuits and systems.

  • 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010

    ISCAS is a unique conference dealing with circuits and systems. It's the yearly "rendez-vous" of leading researchers, coming both from academia and industry, in the highly active fields of theory, design and implementation of circuits and systems. The Symposium will focus on circuits and systems for high quality life and consumer technologies, including mobile communications, advanced multimedia systems, sensor networks and Nano-Bio Circuit Fabrics and Systems.

  • 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

    Analog Signal Processing, Biomedical Circuits and Systems, Blind Signal Processing, Cellular Neural Networks and Array Computing, Circuits and Systems for Communications, Computer-Aided Network Design, Digital Signal Processing, Life-Science Systems and Applications, Multimedia Systems and Applications, Nanoelectronics and Gigascale Systems, Neural Systems and Applications, Nonlinear Circuits and Applications, Power Systems and Power Electronic Circuits, Sensory Systems, Visual Signal Processing and Communi

  • 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008


2013 IEEE 10th International Conference on ASIC (ASICON 2013)

I. Design Techniques[1] VLSI Design and Circuits[2] Analog, Mixed Signal and RF Circuits[3] Application-Specific SoCs[4] Circuits and Systems for Wireless Communications [5] Testing, Reliability, Fault-Tolerance[6] Advanced MemoryII. CAD Techniques[7] Circuits Simulation, Synthesis, Verification and Physical design[8] CAD for system, Design for Manufacturing and TestingIII. New Techniques, new processing, new devices and their applications[9] MEMS Techniques[10] Nanoelectronics and Gigascale systems[11] New Devices: Hetrojunction Devices, Fin FET, CNT MTJ Devices,, 3-D integration, etc..[12] Advanced Interconnection Technology, High K/Metal gate technology and other VLSL New Processing, New technologies .[13] VLSI application for Energy generation, conservation and control,IC Design, Analog Circuit, Mixed Signal & RF Circuits, SOC, Wireless Communication, IC Testing, Reliebility, CAD Techniques, Synthesis, Verification, Physical Design, DMF, Memory, MEMS, 3D IC, High K/


2013 IEEE 11th International Conference on Electronic Measurement & Instruments (ICEMI)

ICEMI is invited authors to submit original papers in any but not limited as following areas: Science Foundation of Instrument and Measurement Innovative Designing of Instrument and Test System Applications on Instrument and Testing Signal & Image Processing Sensor and Non-electric Measurement Communication and Network Test Systems Control Theory and Application Condition Monitoring, Fault Diagnosis and Prediction Other Relevant Theories and Technologies


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Periodicals related to SDRAM

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Broadcasting, IEEE Transactions on

Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


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Most published Xplore authors for SDRAM

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Xplore Articles related to SDRAM

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An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003., 2003

We present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy ...


Pipeline controller on dynamic memory access policy

2011 International Conference on Electronics, Communications and Control (ICECC), 2011

This paper presents a novel pipeline memory controller based on multi-core network processing. This pipeline controller includes six level pipeline operations which can reduce access latency and provide bank and row address relationship of two adjacent instructions in advance. The controller would take a dynamic memory access policy according to the address relationship got from the pipelines operations. The traditional ...


Assembly process development of stacked multi-chip leadframe package

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971), 2004

Driven by customer requirements and the need for cost reduction, high density stacked multi-chip package (MCP) based on leadframe type has been developed in Agere Systems. This MCP integrates one SoC chip with two stacked SDRAM chips. The paper focuses on the assembly process development and finite element analysis of high density multi-chip package based on leadframe. All the experiments ...


DeviceNet master research based on embedded system

The 2nd International Conference on Information Science and Engineering, 2010

Analyzing several commonly used DeviceNet networks, this thesis proposes the master application system based on embedded system. The system's embedded platform is made up of ARM9 and WindowsCE.Net, it implements the driver program of the DeviceNet communication interface, the application program of network management and scanner. The system built for modern breeding environment monitor successfully; thereby an easy, high reliable ...


OC-48 generic frame mapping device for WAN accessing

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings., 2004

For the transmit quality and convenience of the storage area network (SAN) or local area network (LAN) in the wide area network (WAN), we designed a generic frame mapping (GFM) device to carry the SAN or LAN data onto the SDH/SONET network. The SAN devices which contain the fiber channel or the gigabit Ethernet interface can connect with our GFM ...


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Educational Resources on SDRAM

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IEEE.tv Videos

No IEEE.tv Videos are currently tagged "SDRAM"

IEEE-USA E-Books

  • An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems

    We present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy as well as program execution time. This bus utilization predictor reduces memory energy consumption without the expense of increasing program execution time. It achieved the performance level of open page policy by consuming 20% less of memory energy.

  • Pipeline controller on dynamic memory access policy

    This paper presents a novel pipeline memory controller based on multi-core network processing. This pipeline controller includes six level pipeline operations which can reduce access latency and provide bank and row address relationship of two adjacent instructions in advance. The controller would take a dynamic memory access policy according to the address relationship got from the pipelines operations. The traditional memory controller usually takes a static memory access policy which is applicable to only bank interleaving optimization or page hit optimization. Unlike the traditional controller, the pipeline controller could take both bank interleaving and page hit optimization in the same memory system under the dynamic access policy-Open Page (OP) or Close Page Autoprecharge (CPA)<sup>[1]</sup>. The performance analysis shows that this pipeline memory controller can reduce memory access latency and the improved the throughput greatly when compared with traditional memory controller.

  • Assembly process development of stacked multi-chip leadframe package

    Driven by customer requirements and the need for cost reduction, high density stacked multi-chip package (MCP) based on leadframe type has been developed in Agere Systems. This MCP integrates one SoC chip with two stacked SDRAM chips. The paper focuses on the assembly process development and finite element analysis of high density multi-chip package based on leadframe. All the experiments in the paper were conducted using a test vehicle with 144 pin TQFP leadframe. Three main processes were evaluated in the experiments, which are die attach, wire bonding and molding. The paper presents some of the challenges for process development such as placement accuracy and epoxy bleed for die attach, ball neck nicking and wire straightness control of reverse bonding for wire bonding and wire sweep for molding. The evaluation results for these three processes are satisfactory. The paper also presents finite element modeling for both stacked MCP and discrete single die packages. The results show that there is no obvious difference on package warpage and thermal/mechanical stress for both packages. Therefore, it is verified that the new established processes for this stacked MCP could be used for actual stacked MCP prototypes build and this stacked MCP is promising for future high volume production.

  • DeviceNet master research based on embedded system

    Analyzing several commonly used DeviceNet networks, this thesis proposes the master application system based on embedded system. The system's embedded platform is made up of ARM9 and WindowsCE.Net, it implements the driver program of the DeviceNet communication interface, the application program of network management and scanner. The system built for modern breeding environment monitor successfully; thereby an easy, high reliable and low-cost fieldbus solution is achieved.

  • OC-48 generic frame mapping device for WAN accessing

    For the transmit quality and convenience of the storage area network (SAN) or local area network (LAN) in the wide area network (WAN), we designed a generic frame mapping (GFM) device to carry the SAN or LAN data onto the SDH/SONET network. The SAN devices which contain the fiber channel or the gigabit Ethernet interface can connect with our GFM device easily. This work presents the function and architecture of each unit in our GFM device.

  • A real-time compressing method for complex SAR images

    Complex image compression is widely used in diverse remote sensing applications in order to reduce the costs of data storage and release the burden of data transmission on limited data transmission channels. However, the huge amount of data makes it difficult to compress in real-time. A novel real-time compressing method for complex SAR images is presented in this paper. The system uses a fixed-point DSP of TI SM320c6416 with IGB SDRAM (synchronous dynamic random access memory). After removing the redundancy of complex image in frequency domain, arithmetic codec is applied for statistical redundancy, further. With the least data regress limes, good performance is achieved. The results show that compressing a complex image of 8192*2048 needs only 4315 ms in an acceptable distortion with compression ratio of 16.214:1. So, the method is highly suitable for real-time (or low delay) applications.

  • A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test

    An experimental chip for a 32b wide DDR2 SDRAM interface for SoC is fabricated in a 90nm CMOS process and achieves 960Mb/s/pin operation. Impedance- calibration circuits and flexible round-trip circuits in a continuous-adaptive DDR2 interface are used to suppress skew and allow a longer round-trip time.

  • Synthesis and estimation of memory interfaces for FPGA-based reconfigurable computing engines

    As the densities of current FPGA continue to grow it is now possible to generate System-On-a-Chip (SoC) designs where multiple computing cores are connected to various memory modules with customized topology with application specific memory access patterns. For example, Xilinx has recently introduced devices to which a paired down version of a PowerPC core can be mapped and connected to a set of internal memories. In this paper we address the problem of synthesizing and estimating the area and speed of memory interfacing for Static RAM (SRAM) and Synchronous Dynamic RAM (SDRAM) with various latency parameters and access modes. We describe a set of synthesizable and programmable memory interfaces a compiler can use to automatically generate the appropriate designs for mapping computations to FPGA-based architectures. Our preliminary results reveal that it is possible to accurately model the area and timing requirements using a linear estimation function. We have successfully integrated the proposed memory interface designs with simple image processing kernels generated using commercially available behavioral synthesis tools.

  • FPGA-Based Expanded Circuit Design for DSP Signal Processing

    In a digital control system for magnetic bearings, because of factors such as switching currents of a power amplifier, an input signal of the system will be mixed with noise and the signal should be filtered. If the sampling rate of the system for the input signal is not high enough, a filter used will introduce a large delay between its output and input signal. To solve this problem, one way is to sample the input signal multiple times at the beginning of every control period and get a filtered signal by average methods. Then the response speed of the bearing controller would not be influenced. A FPGA-based expanded circuit was designed for this purpose and it was added to a DSP control board as a component of the control platform. Without increasing computational burden of the DSP, the FPGA obtained oversampled signals and processed them by its rich on-chip resources. Meanwhile, in order to view the sampled signals and monitor the system online, the circuit was also equipped with a SDRAM to store the sampled data. This design had a simple structure and reliable performance. Experimental results showed that the circuit could achieve the required signal oversampling and the subsequent data processing and the signal noise was effectively reduced.

  • Design of arbitrary waveform generator based on SDRAM

    To solve the problems of the difficulty to generate long period waveform, of the complicated operation and inconvenient control, a scheme that is based on the combination of large capacity storage and virtual instruments technique of arbitrary waveform generator (AWG), is proposed. The storage capacity has been raised up to 8M by utilizing synchronous DRAM (SDRAM) as a waveform data memory; in the meantime, a friendly and easy control instrument interface is finished with the help of LabVIEW. Because of hard control of SDRAM, the FPGA is especially employed to solve the problem of SDRAM control and timing- logical control of the whole system; it not only improves data access speed but also enhances the whole system's integration capability, as well as anti- interference ability. The design of SDRAM controller and instrument interface is given in detail. Testing data of experimental prototype can meet the design targets. It has great practical value.



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