Conferences related to SDRAM

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2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.


2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAMs22. Phase Change Memory23. 3-Dimensional Memory24. MEMS Technology25. Thin Film Transistors26. Biosensors27. PV and Energy Harvesting28. Front End of Line (FEOL) R

  • 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

    Silicon IC, Silicon/germanium devices , Interconnect , Low K and High Kdielectric , Advance Memories , nano -electronics, Organic and Compound semiconductor devices ,sensors and MEMS, Semiconductor material erization, Reliability , Modeling and simulation,Packaging and testing , Digital, Analog, Mixed Signal IC and SOC design technology,Low -power, RF devices & circuits, ICCAD

  • 2010 IEEE 10th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

    Silicon IC, Silicon/germanium devices , Interconnect , Low K and High K dielectric , Advance Memories , nano-electronics, Organic and Compound semiconductor devices , sensors and MEMS, Semiconductor material characterization, Reliability , Modeling and simulation, Packaging and testing , Digital, Analog, Mixed Signal IC and SOC design technology,Low-power, RF devices & circuits, IC CAD .


2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems.ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.

  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS)

    The Symposium will focus on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability. The ISCAS 2010 will include oral and poster sessions; tutorials given by experts in state-of-the-art topics; and special sessions, with the aim of complementing the regular program with topics of particular interest to the community that cut across and beyond disciplines traditionally represented at ISCAS.

  • 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012

    2012 International Symposium on Circuits and Systems (ISCAS 2012) aims at providing the world's premier forum of leading researchers in circuits and systems areas from academia and industries, especially focusing on Convergence of BINET (BioInfoNanoEnviro Tech.) which represents IT, NT and ET and leading Human Life Revolutions. Prospective authors are invited to submit papers of their original works emphasizing contributions beyond the present state of the art. We also welcome proposals on special tuto

  • 2011 IEEE International Symposium on Circuits and Systems (ISCAS)

    The IEEE International Symposium on Circuits and Systems (ISCAS) is the world's premier networking forum of leading researchers in the highly active fields of theory, design and implementation of circuits and systems.

  • 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010

    ISCAS is a unique conference dealing with circuits and systems. It's the yearly "rendez-vous" of leading researchers, coming both from academia and industry, in the highly active fields of theory, design and implementation of circuits and systems. The Symposium will focus on circuits and systems for high quality life and consumer technologies, including mobile communications, advanced multimedia systems, sensor networks and Nano-Bio Circuit Fabrics and Systems.

  • 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

    Analog Signal Processing, Biomedical Circuits and Systems, Blind Signal Processing, Cellular Neural Networks and Array Computing, Circuits and Systems for Communications, Computer-Aided Network Design, Digital Signal Processing, Life-Science Systems and Applications, Multimedia Systems and Applications, Nanoelectronics and Gigascale Systems, Neural Systems and Applications, Nonlinear Circuits and Applications, Power Systems and Power Electronic Circuits, Sensory Systems, Visual Signal Processing and Communi

  • 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008


2013 IEEE 10th International Conference on ASIC (ASICON 2013)

I. Design Techniques[1] VLSI Design and Circuits[2] Analog, Mixed Signal and RF Circuits[3] Application-Specific SoCs[4] Circuits and Systems for Wireless Communications [5] Testing, Reliability, Fault-Tolerance[6] Advanced MemoryII. CAD Techniques[7] Circuits Simulation, Synthesis, Verification and Physical design[8] CAD for system, Design for Manufacturing and TestingIII. New Techniques, new processing, new devices and their applications[9] MEMS Techniques[10] Nanoelectronics and Gigascale systems[11] New Devices: Hetrojunction Devices, Fin FET, CNT MTJ Devices,, 3-D integration, etc..[12] Advanced Interconnection Technology, High K/Metal gate technology and other VLSL New Processing, New technologies .[13] VLSI application for Energy generation, conservation and control,IC Design, Analog Circuit, Mixed Signal & RF Circuits, SOC, Wireless Communication, IC Testing, Reliebility, CAD Techniques, Synthesis, Verification, Physical Design, DMF, Memory, MEMS, 3D IC, High K/

  • 2011 IEEE 9th International Conference on ASIC (ASICON 2011)

    Design Techniques;VLSI Design and Circuits;Analog, Mixed Signal and RF Circuits;Application-Specific SoCs;Circuits and Systems for Wireless Communications;Testing, Reliability, Fault-Tolerance;Advanced Memory;CAD Techniques;Circuits Simulation, Synthesis, Verification and Physical design;CAD for system, Design for Manufacturing and Testing;Emerging Applications and New Technologies;MEMS Techniques;Nanoelectronics and Gigascale systems; New Devices Hetro-integration, 3-D integration;VLSL New Processing, New

  • 2009 IEEE 8th International Conference on ASIC (ASICON 2009)

    Analog Integrated Circuits Design, Digital Integrated Circuits Design, RF IC Design, Digital Signal Processing, Mixed-Signal IC , Applcation-Specific SOCs, Low Power IC, FPGA, Embedded Processors, Circuits for Wireless Communications, Flash Memory, Ferroelectric Memory, Resistive Switching Memory, Phase Change Memory, Design for testing, Design for Manufacturing, CMOS reliebility, CAD tools, MEMS, NEMS

  • 2007 7th International Conference on ASIC (ASICON 2007)

  • 2005 6th International Conference on ASIC (ASICON 2005)


2013 IEEE 11th International Conference on Electronic Measurement & Instruments (ICEMI)

ICEMI is invited authors to submit original papers in any but not limited as following areas: Science Foundation of Instrument and Measurement Innovative Designing of Instrument and Test System Applications on Instrument and Testing Signal & Image Processing Sensor and Non-electric Measurement Communication and Network Test Systems Control Theory and Application Condition Monitoring, Fault Diagnosis and Prediction Other Relevant Theories and Technologies

  • 2011 IEEE 10th International Conference on Electronic Measurement & Instruments (ICEMI)

    ICEMI is the world s premier conference dedicated to the electronic test of devices, boards and systems covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement, and is convened every two years. The purpose of the ICEMI is to provide excellent opportunities for scientists, engineers, and participants throughout the world to present the latest research results and to exchange their views or experience.

  • 2009 9th International Conference on Electronic Measurement & Instruments (ICEMI 2009)

    Science Foundation of Instrument and Measurement Instrument, Measurement and Test Technology: Sensing Technology and Transducer Designing of Instrument and Test System Applications on Instrument and Testing: Communication and Network Test Systems Control Theory and Application

  • 2007 8th International Conference on Electronic Measurement & Instruments (ICEMI 2007)


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Periodicals related to SDRAM

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...




Xplore Articles related to SDRAM

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Analysis and comparison of DDR3/DDR4 clock duty-cycle-distortion (DCD) for UDIMM and discrete SDRAM component configurations

Gawon Kim; June Feng; Marjan Mokhtaari; Janmejay Adhyaru; Raheel Shaikh; Balaji Natarajan; Dan Oh IEEE Electromagnetic Compatibility Magazine, 2016

In this paper, the clock duty cycle distortion (DCD) jitter will be investigated and the results will be compared for two channel configurations: using a general UDIMM topology and using discrete SDRAM component topology. These channel configurations will be simulated and analyzed for ISI effects, such as channel loss and reflection. The outcome of this investigation will show the primary ...


Demo: Real-time depth extraction and viewpoint interpolation on FPGA

Guanyu Yi; Hsiu-Chi Yeh; Geert Vanmeerbeeck; Ke Zhang; Gauthier Lafrait 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

In this demo, we demonstrate a real-time viewpoint interpolation application on FPGA. Viewpoint interpolation is the process of synthesizing plausible in- between views - so-called virtual camera views - from a couple of surrounding fixed camera views. Stereo matching is used to extract depth information, by computing a disparity map from a pair of input images. With the depth information, ...


Research and application of embedded technology in remote network monitoring system of coal mine

Zhang Xiaodong; Tan Yuegang; Hou Yan The 26th Chinese Control and Decision Conference (2014 CCDC), 2014

Aiming at the weakness and deficiency of current coal mine monitoring system, this paper discusses the design and implementation of a platform to remotely monitor and control coal mine production processes over Industrial Ethernet by using the embedded technology. Integrated with each lower computer terminal are S3C2410 microprocessors that can be used for connectivity to the monitoring network effectively. Besides ...


1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

H. Fujisawa; M. Nakamura; Y. Takai; Y. Koshikawa; T. Matano; S. Narui; N. Usuki; C. Dono; S. Miyatake; M. Morino; K. Arai; S. Kubouchi; I. Fujii; H. Yoko; T. Adachi IEEE Journal of Solid-State Circuits, 2005

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual- clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one- shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; ...


High performance JPEG decoder based on FPGA

Junming Shan; Duyao Wang; Eryan Yang 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, 2011

This paper describes designing a realtime Joint Photographic Experts Group (JPEG) decoder which is capable of high definition images decoding and realized in a Xilinx Vertex 5 Field Programmable Gate Array (FPGA). We propose a highly efficient pipelining FPGA implementation of the two-dimensional inverse discrete cosine transformation. Ping-pong buffer is introduced in order to improve decoding performance. This JPEG decoder ...


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Educational Resources on SDRAM

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eLearning

Analysis and comparison of DDR3/DDR4 clock duty-cycle-distortion (DCD) for UDIMM and discrete SDRAM component configurations

Gawon Kim; June Feng; Marjan Mokhtaari; Janmejay Adhyaru; Raheel Shaikh; Balaji Natarajan; Dan Oh IEEE Electromagnetic Compatibility Magazine, 2016

In this paper, the clock duty cycle distortion (DCD) jitter will be investigated and the results will be compared for two channel configurations: using a general UDIMM topology and using discrete SDRAM component topology. These channel configurations will be simulated and analyzed for ISI effects, such as channel loss and reflection. The outcome of this investigation will show the primary ...


Demo: Real-time depth extraction and viewpoint interpolation on FPGA

Guanyu Yi; Hsiu-Chi Yeh; Geert Vanmeerbeeck; Ke Zhang; Gauthier Lafrait 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

In this demo, we demonstrate a real-time viewpoint interpolation application on FPGA. Viewpoint interpolation is the process of synthesizing plausible in- between views - so-called virtual camera views - from a couple of surrounding fixed camera views. Stereo matching is used to extract depth information, by computing a disparity map from a pair of input images. With the depth information, ...


Research and application of embedded technology in remote network monitoring system of coal mine

Zhang Xiaodong; Tan Yuegang; Hou Yan The 26th Chinese Control and Decision Conference (2014 CCDC), 2014

Aiming at the weakness and deficiency of current coal mine monitoring system, this paper discusses the design and implementation of a platform to remotely monitor and control coal mine production processes over Industrial Ethernet by using the embedded technology. Integrated with each lower computer terminal are S3C2410 microprocessors that can be used for connectivity to the monitoring network effectively. Besides ...


1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

H. Fujisawa; M. Nakamura; Y. Takai; Y. Koshikawa; T. Matano; S. Narui; N. Usuki; C. Dono; S. Miyatake; M. Morino; K. Arai; S. Kubouchi; I. Fujii; H. Yoko; T. Adachi IEEE Journal of Solid-State Circuits, 2005

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual- clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one- shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; ...


High performance JPEG decoder based on FPGA

Junming Shan; Duyao Wang; Eryan Yang 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, 2011

This paper describes designing a realtime Joint Photographic Experts Group (JPEG) decoder which is capable of high definition images decoding and realized in a Xilinx Vertex 5 Field Programmable Gate Array (FPGA). We propose a highly efficient pipelining FPGA implementation of the two-dimensional inverse discrete cosine transformation. Ping-pong buffer is introduced in order to improve decoding performance. This JPEG decoder ...


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