Conferences related to Programmable circuits

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2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems

The conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation (EDA), embedded systems, and enabling technologies. It covers the entire spectrum of activities in the two vital areas of very large scale integration (VLSI) and embedded systems, which underpin the semiconductor industry.


2012 19th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2012)

The IEEE International Conference on Electronics, Circuits, and Systems (ICECS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society in Region 8 of IEEE (Europe, Middle East, and Africa). It annually presents papers from the whole world on design methodologies, techniques, and experimental results in emerging electronics, circuits, and systems topics.

  • 2011 18th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2011)

    ICECS presents design methodologies, techniques, and experimental results in emerging electronics, circuits, and systems topics. ICECS 2011 will cover all aspects of the fields of electronics circuits and systems, including analog and digital electronics, solid-state circuits, power, high-speed, automotive, biomedical, and signal processing.

  • 2010 17th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2010)

    ICECS is the flagship conference of the IEEE Circuits and Systems (CAS) Society in Region 8 of IEEE (Europe, Middle East, and Africa). It annually presents papers from the whole world on design methodologies, techniques, and experimental results in emerging electronics, circuits, and systems topics.

  • 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

    The IEEE International Conference on electronics, Circuits, and Systems (ICECS)is the flagship conference of the IEEE Circuits & Systems (CAS) Society in Region 8 (Europe, Middle East and Africa). It presents design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. ICECS 2009 will include tutorials, regular sessions (lecture and poster), special sessions and exhibitions.

  • 2008 15th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2008)

    ICECS is a major international forum presenting design methodologies, techniques and experimental results in emerging electronics, circuits and smart systems topics. ICECS has developed into the flagship conference of the IEEE CAS Society in Region 8, with participants from all over the world. The conference will include regular, special and poster sessions.

  • 2007 14th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2007)

    ICECS is a major international forum presenting design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. Topics include: Analog/Digital Circuits, and Signal Processing, Sensing and Sensor Networks, Telecommunications and Multimedia, RF and Wireless Circuits & Systems, Photonic and Optoelectronic Circuits, Biomedical Circuits & Systems, Test and Reliability System Architectures and Applications, Neural Network Circuits & Systems, Design Automation of Ele


2012 MIXDES - 19th International Conference "Mixed Design of Integrated Circuits & Systems"

The MIXDES Conference covers research in design, modeling, simulation, testing and manufacturing in various areas such as micro - and nanoelectronics, semiconductors, sensors, actuators and power devices.



Periodicals related to Programmable circuits

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...




Xplore Articles related to Programmable circuits

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Exploring multistage interconnection network implementations for FPGA-based MPSOCs

Aydi, Y.; Tligue, R.; Abid, M.; Dekeyser, J. Design and Test Workshop (IDT), 2009 4th International, 2009

Modern embedded systems integrated a variety of complex and heterogeneous components communicating with each other at high-speed rates. The interconnection architecture employed in such systems has an important impact to their overall performance. Multistage interconnection network has emerged as a promising alternative to ensure communication for multiprocessor system on chips. In this paper, we describe a design methodology of MIN-based ...


Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit

Matrosova, A.; Ostanin, S.; Kirienko, I. Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on, 2015

The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved Configurable Logic Blocks (CLBs) based on Look Up Tables (LUTs) that may mask a gate fault. The suggested approach in comparison with the currently in use ones ...


Simultaneous state encoding and communication cost optimization for FSM net design

Koegst, M.; Grass, W.; Franke, G.; Feske, K. EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference., 1994

Linear partitioning is a very attractive method for designing an FSM as a net of cooperating FSMs. For a better exploitation of its inherent potency we introduce (1) a method that reduces the communication overhead to control the cooperation between the subFSMs and (2) a new global solution for the binary encoding problem for both states and communication signals. Experimental ...


Class of memristors from cascade of static nonlinear two ports with dynamic one-ports

Ascoli, A.; Tetzlaff, R.; Corinto, F. Neural Networks (IJCNN), 2015 International Joint Conference on, 2015

A class of memristor circuits is obtained by cascading a static nonlinear two- port with a dynamical one-port. The terminals of the input port of the static nonlinearity represent the access nodes for each memristor in the class. The class may be splitted into two sub-classes, namely the current- and voltagecontrolled memristors. Two further sets of memristors may be identied ...


A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner

Hong-Yi Huang; Jian-Hong Shen Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on, 2004

In this work, a DLL-based CMOS programmable clock generator is presented. A threshold-trigger delay element obtains better duty cycle and jitter performance without dc power consumption. A programmable edge combiner using circular scheme can operate at 0.8V supply voltage. A clock generator programmed by 1, 2, 3 and 6 is design using a 0.18-um 1p6m CMOS process. The input and ...


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Educational Resources on Programmable circuits

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eLearning

Exploring multistage interconnection network implementations for FPGA-based MPSOCs

Aydi, Y.; Tligue, R.; Abid, M.; Dekeyser, J. Design and Test Workshop (IDT), 2009 4th International, 2009

Modern embedded systems integrated a variety of complex and heterogeneous components communicating with each other at high-speed rates. The interconnection architecture employed in such systems has an important impact to their overall performance. Multistage interconnection network has emerged as a promising alternative to ensure communication for multiprocessor system on chips. In this paper, we describe a design methodology of MIN-based ...


Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit

Matrosova, A.; Ostanin, S.; Kirienko, I. Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on, 2015

The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved Configurable Logic Blocks (CLBs) based on Look Up Tables (LUTs) that may mask a gate fault. The suggested approach in comparison with the currently in use ones ...


Simultaneous state encoding and communication cost optimization for FSM net design

Koegst, M.; Grass, W.; Franke, G.; Feske, K. EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference., 1994

Linear partitioning is a very attractive method for designing an FSM as a net of cooperating FSMs. For a better exploitation of its inherent potency we introduce (1) a method that reduces the communication overhead to control the cooperation between the subFSMs and (2) a new global solution for the binary encoding problem for both states and communication signals. Experimental ...


Class of memristors from cascade of static nonlinear two ports with dynamic one-ports

Ascoli, A.; Tetzlaff, R.; Corinto, F. Neural Networks (IJCNN), 2015 International Joint Conference on, 2015

A class of memristor circuits is obtained by cascading a static nonlinear two- port with a dynamical one-port. The terminals of the input port of the static nonlinearity represent the access nodes for each memristor in the class. The class may be splitted into two sub-classes, namely the current- and voltagecontrolled memristors. Two further sets of memristors may be identied ...


A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner

Hong-Yi Huang; Jian-Hong Shen Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on, 2004

In this work, a DLL-based CMOS programmable clock generator is presented. A threshold-trigger delay element obtains better duty cycle and jitter performance without dc power consumption. A programmable edge combiner using circular scheme can operate at 0.8V supply voltage. A clock generator programmed by 1, 2, 3 and 6 is design using a 0.18-um 1p6m CMOS process. The input and ...


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Standards related to Programmable circuits

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