Conferences related to Logic gates

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2018 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2016 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2014 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 IEEE Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices


2013 Design, Automation & Test in Europe Conference & Exhibition (DATE 2013)

DATE is the complete event for the European electronic and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with approximately 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.

  • 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)

    DATE is the complete event for the European electronic system and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with some 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.

  • 2011 Design, Automation & Test in Europe Conference & Exhibition (DATE 2011)

    DATE is the complete event for the European electronic system and test community. A world leading conference and exhibition, DATE unites 2,000 professionals with some 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.

  • 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

    All aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems.

  • 2008 Design, Automation & Test in Europe Conference & Exhibition (DATE 2008)

    The 11th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software. The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials.


2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.

  • 2008 IEEE International Integrated Reliability Workshop (IRW)

    The workshop focuses on ensuring device reliability through fabrication, design, testing, characterization and simulation as well as identification of the defects and mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing and sharing reliability technology and test methodology.


2013 Workshop on RTL and High Level Testing (WRTLT)

The purpose of this workshop is to bring researchers and practitioners of LSI testing from allover the world together to exchange ideas and experiences in register transfer level (RTL) andhigh level testing.


2011 International Workshop on Dielectric Thin Films for Future ULSI Devices: Science and Technology (IWDTF)

The IWDTF2011 will focus on the science and technologies of gate dielectric films for MOS and memory devices, such as ultrathin SiO2, SiON, high-k gate dielectrics, and ferroelectric films. The topics on other technologies involved in the advanced gate stacks, including metal gate electrodes and high-mobility channel materials, will also be discussed.


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Periodicals related to Logic gates

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Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Magnetics, IEEE Transactions on

Science and technology related to the basic physics and engineering of magnetism, magnetic materials, applied magnetics, magnetic devices, and magnetic data storage. The Transactions publishes scholarly articles of archival value as well as tutorial expositions and critical reviews of classical subjects and topics of current interest.


Nanotechnology, IEEE Transactions on

The proposed IEEE Transactions on Nanotechnology will be devoted to the publication of manuscripts of archival value in the general area of nanotechnology, that is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.


Quantum Electronics, IEEE Journal of

Generation, amplification, modulation, detection, waveguiding, or techniques and effects that can affect the propagation characteristics of coherent electromagnetic radiation having submillimeter and shorter wavelengths


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Most published Xplore authors for Logic gates

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Xplore Articles related to Logic gates

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A review on design of improved high performance of high valency Ling adder

Bharti Tiple; Rupali Suraskar 2016 World Conference on Futuristic Trends in Research and Innovation for Social Welfare (Startup Conclave), 2016

Two-operand binary addition is the most widely used arithmetic operation in modern data path designs. Parallel prefix adders are used for economical VLSI implementation of binary variety additions. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. The look and implementation details for such lower complex quick parallel prefix adders supported ...


Effective channel length in Junctionless Nanowire Transistors

Renan Trevisoli; Rodrigo T. Doria; Michelly de Souza; Marcelo A. Pavanello 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro), 2015

The aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the ...


14nm FinFET device electronic study

Xinyun Xie; Jianhua Ju 2016 China Semiconductor Technology International Conference (CSTIC), 2016

In this paper, wafers with (100) substrate and standard notch orientation were used. Our results showed that the mobility for FinFET PMOS device is almost 2 times higher than for the planar device, mainly due to the benefit from the (110) sidewalls channel. The CV curve showed the good quality of the gate dielectric. DIBL is 24mv/v and 72mv/decade for ...


High-Throughput Screening of Amorphous <formula formulatype="inline"><tex Notation="TeX">$hbox{Y}_{2} hbox{O}_{3}$</tex></formula>&#x2013;<formula formulatype="inline"><tex Notation="TeX">$hbox{TiO}_{2}hbox{/}hbox{SiO}_{2}$</tex> </formula> Higher <formula formulatype="inline"><tex Notation="TeX">$kappa$</tex></formula> Gate Dielectric Layers

Kao-Shuo Chang; Martin L. Green; Peter K. Schenck; Igor Levin; Eswaranand Venkatasubramanian IEEE Transactions on Electron Devices, 2012

In this paper, an approach using native SiO2 to make amorphous higher dielectric constant films based on the Y2O3-TiO2/SiO2/Si compositional spread libraries by combinatorial pulsed laser deposition is reported. The key feature of the experiment is that combinatorial methodology is used to quickly screen the potential high-dielectric-constant films out of a large composition parameter space. Scanning X-ray microdiffractometry and high-resolution ...


Adaptation of the pedagogical approaches for master students in microelectronics in the frame of a French-Chinese joint program

O. Bonnaud; Xuefei Zhong 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro), 2015

In the Far-East there are more and more international joint programs between local universities and occidental academic institutions. In the field of microelectronics, joint masters were set-up. The aim is to form on both sides the students in order to give them the skills and the know-how adapted to economic world. The paper deals with the difference of culture based ...


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Educational Resources on Logic gates

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eLearning

A review on design of improved high performance of high valency Ling adder

Bharti Tiple; Rupali Suraskar 2016 World Conference on Futuristic Trends in Research and Innovation for Social Welfare (Startup Conclave), 2016

Two-operand binary addition is the most widely used arithmetic operation in modern data path designs. Parallel prefix adders are used for economical VLSI implementation of binary variety additions. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. The look and implementation details for such lower complex quick parallel prefix adders supported ...


Effective channel length in Junctionless Nanowire Transistors

Renan Trevisoli; Rodrigo T. Doria; Michelly de Souza; Marcelo A. Pavanello 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro), 2015

The aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the ...


14nm FinFET device electronic study

Xinyun Xie; Jianhua Ju 2016 China Semiconductor Technology International Conference (CSTIC), 2016

In this paper, wafers with (100) substrate and standard notch orientation were used. Our results showed that the mobility for FinFET PMOS device is almost 2 times higher than for the planar device, mainly due to the benefit from the (110) sidewalls channel. The CV curve showed the good quality of the gate dielectric. DIBL is 24mv/v and 72mv/decade for ...


High-Throughput Screening of Amorphous <formula formulatype="inline"><tex Notation="TeX">$hbox{Y}_{2} hbox{O}_{3}$</tex></formula>&#x2013;<formula formulatype="inline"><tex Notation="TeX">$hbox{TiO}_{2}hbox{/}hbox{SiO}_{2}$</tex> </formula> Higher <formula formulatype="inline"><tex Notation="TeX">$kappa$</tex></formula> Gate Dielectric Layers

Kao-Shuo Chang; Martin L. Green; Peter K. Schenck; Igor Levin; Eswaranand Venkatasubramanian IEEE Transactions on Electron Devices, 2012

In this paper, an approach using native SiO2 to make amorphous higher dielectric constant films based on the Y2O3-TiO2/SiO2/Si compositional spread libraries by combinatorial pulsed laser deposition is reported. The key feature of the experiment is that combinatorial methodology is used to quickly screen the potential high-dielectric-constant films out of a large composition parameter space. Scanning X-ray microdiffractometry and high-resolution ...


Adaptation of the pedagogical approaches for master students in microelectronics in the frame of a French-Chinese joint program

O. Bonnaud; Xuefei Zhong 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro), 2015

In the Far-East there are more and more international joint programs between local universities and occidental academic institutions. In the field of microelectronics, joint masters were set-up. The aim is to form on both sides the students in order to give them the skills and the know-how adapted to economic world. The paper deals with the difference of culture based ...


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IEEE-USA E-Books

  • Combinational Circuits

    This chapter contains sections titled: Introduction to Digital Circuits Binary Numbers: a Quick Introduction Boolean Algebra Minterms: Standard or Canonical Sum of Products (SOP) Form Maxterms: Standard or Canonical Product of Sums (POS) Form Karnaugh Maps and Design Examples Product of Sums Simplifications Don't Care Conditions Logic Gates: Electrical and Timing Characteristics Summary Further Reading Problems

  • Quantum Gates and Circuits

    This chapter contains sections titled: Classical Logic Gates Single-Qubit Gates More Single-Qubit Gates Exponentiation The Z-Y Decomposition Basic Quantum Circuit Diagrams Controlled Gates Gate Decomposition Exercises

  • No title

    This book, Electronic Devices and Circuit Application, is the first of four books of a larger work, Fundamentals of Electronics. It is comprised of four chapters describing the basic operation of each of the four fundamental building blocks of modern electronics: operational amplifiers, semiconductor diodes, bipolar junction transistors, and field effect transistors. Attention is focused on the reader obtaining a clear understanding of each of the devices when it is operated in equilibrium. Ideas fundamental to the study of electronic circuits are also developed in the book at a basic level to lessen the possibility of misunderstandings at a higher level. The difference between linear and non-linear operation is explored through the use of a variety of circuit examples including amplifiers constructed with operational amplifiers as the fundamental component and elementary digital logic gates constructed with various transistor types. Fundamentals of Electronics has been designed prima ily for use in an upper division course in electronics for electrical engineering students. Typically such a course spans a full academic years consisting of two semesters or three quarters. As such, Electronic Devices and Circuit Applications, and the following two books, Amplifiers: Analysis and Design and Active Filters and Amplifier Frequency Response, form an appropriate body of material for such a course. Secondary applications include the use in a one-semester electronics course for engineers or as a reference for practicing engineers.

  • No title

    PSpice for Circuit Theory and Electronic Devices is one of a series of five PSpice books and introduces the latest Cadence Orcad PSpice version 10.5 by simulating a range of DC and AC exercises. It is aimed primarily at those wishing to get up to speed with this version but will be of use to high school students, undergraduate students, and of course, lecturers. Circuit theorems are applied to a range of circuits and the calculations by hand after analysis are then compared to the simulated results. The Laplace transform and the s-plane are used to analyze CR and LR circuits where transient signals are involved. Here, the Probe output graphs demonstrate what a great learning tool PSpice is by providing the reader with a visual verification of any theoretical calculations. Series and parallel-tuned resonant circuits are investigated where the difficult concepts of dynamic impedance and selectivity are best understood by sweeping different circuit parameters through a range of values. O taining semiconductor device characteristics as a laboratory exercise has fallen out of favour of late, but nevertheless, is still a useful exercise for understanding or modelling semiconductor devices. Inverting and non-inverting operational amplifiers characteristics such as gain-bandwidth are investigated and we will see the dependency of bandwidth on the gain using the performance analysis facility. Power amplifiers are examined where PSpice/Probe demonstrates very nicely the problems of cross-over distortion and other problems associated with power transistors. We examine power supplies and the problems of regulation, ground bounce, and power factor correction. Lastly, we look at MOSFET device characteristics and show how these devices are used to form basic CMOS logic gates such as NAND and NOR gates.

  • No title

    Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementati n of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work

  • Simulation of Mixed SwitchedCapacitor/Digital Networks with SignalDriven Switches

    This paper considers the simulation of mixed switchedcapacitor/digital (SC/D) networks containing capacitors, independent and linear-dependent voltage sources, switches, comparators, and logic gates using a new simulator, SW1TCAP2. The switches, in particular, may be controlled by not only periodic waveforms but also by nonperiodic waveforms from the outputs of comparators and logic gates. The signal-dependent modification of network topology through the comparators, logic gates, and signal-driven switches makes the modeling of various nonlinear switched-capacitor circuits possible. Simulation results for a PCM voice encoder, a sigma-delta modulator, a neural network, and a phase- locked loop (PLL) are presented to demonstrate the flexibility of the approach.

  • Monolithic NMOS Digital Integrated Circuits in 6HSiC

    We report the FIRST digital monolithic integrated circuits in the wide bandgap semiconductor silicon carbide (SiC). These logic gates are implemented in enhancement-mode NMOS using ion implanted MOSFET's with non-self-aligned metal gates. We have fabricated and characterized inverters, NAND and NOR gates, XNOR gates, D-latches, RS flip-flops, binary counters, and half adders. All circuits operate properly from room temperature to over 300°C

  • CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications

    Using a 3.5 $micro;m gate length complementary metal-oxidesemiconductor /silicon-on-sapphire (CMOS/80S) technology, a singlechip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. Each clock period, the chip generates a new digitized sample of a sine wave, whose frequency is variable in 220 steps from dc to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst case environment, including ionizing radiation levels up to 3 x 105 rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory (ROM). The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below  - 65 dDc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.

  • HighTemperature Behavior of MOS Devices

    Bulk-silicon and silicon-on-sapphire (SOS) MOS transistors and CMOS logic gates were characterized at temperatures up to 375° C. The bulk-silicon devices were observed to function only below 300°C; the principal degradation mechanism was found to be current leakage at reverse-biased p-n junctions. SOS devices, whose construction eliminates most of these junctions, showed potentially usable characteristics up to 375°C. However, severe self-heating and significant gate-oxide current leakage were observed in SOS. The fact that recognizable characteristics were observed despite self-heating indicates that SOS deviges may be usable at temperatures well above 375° C.



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